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參數(shù)資料
| 型號： | LM1267NA/NOPB |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 音頻／視頻放大 |
| 英文描述： | 3 CHANNEL, VIDEO PREAMPLIFIER, PDIP24 |
| 封裝： | PLASTIC, DIP-24 |
| 文件頁數(shù)： | 4/20頁 |
| 文件大?。?/td> | 1702K |
| 代理商： | LM1267NA/NOPB |
Functional Description (Continued)
H Flyback: H Flyback is an analog signal input from the
monitor horizontal scan. The “H Blank” section uses this
signal to add horizontal blanking to the output video signal.
This enables the user to blank at the cathodes during hori-
zontal flyback. An optional capacitor and/or resistor to
ground may be needed if noise interferes with the H Flyback
signal.
This feature gives very accurate timing for the horizontal
blanking; however, the flyback signal must be very clean.
There should be no ringing or other noise on the flyback
signal.
R
LIMIT is used to limit the input current into the IC to a typical
value of+1mA during flyback and 100 A during normal
forward scan. For example if an H flyback with a peak of
100V is used, R
LIMIT = 100 k. The internal input impedance
of pin 24 is low to limit the maximum voltage swing at the
input to within the supply rail and ground. The IC interface
circuit creates a digital signal from this waveform, which is
used as the blanking signal at the “Output Buffer Amp”. This
signal adds blanking to the video output signal.
Figure 5
shows the H flyback waveforms and the location of R
LIMIT.A
56 pF capacitor has been added to the H Flyback pin on the
demo board for filtering noise on the H Flyback signal.
H Blank: Some customers may still prefer to use a standard
logic signal for the horizontal blanking. Pin 24 can be
adapted to accept a logic input. It is necessary for the current
flow into pin 24 to reverse for proper operation. Therefore the
logic signal must be AC coupled into pin 24.
Figure 6 shows
the recommended circuit for a logic signal input. The blank
signal must be a positive pulse.
Power Save Mode: There are two modes of power save:
1.
Blanking the video
2.
Turning off most of the power for maximum power sav-
ings.
In the first mode the video is completely blanked. By setting
bit-0 in register 9 to a 1 the video will be completely blanked.
This gives some power savings since there is no beam
current in the monitor. Maximum power saving is obtained in
the second mode. Bits 0 and 1 in register 9 should be set to
a 1. Bit 1 in register 9 turns off the video output stage of the
DS200050-26
FIGURE 4. ABL
DS200050-27
FIGURE 5. H Flyback Input Pulse
DS200050-28
FIGURE 6. Standard Logic H Blank
LM1267
www.national.com
12
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