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參數(shù)資料
| 型號(hào)： | LM2501 |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | Mobile Pixel Link (MPL) Camera Interface Serializer and Deserializer |
| 中文描述： | 移動(dòng)像素鏈路（MPL）的相機(jī)接口串行器和解串 |
| 文件頁(yè)數(shù)： | 8/14頁(yè) |
| 文件大?。?/td> | 302K |
| 代理商： | LM2501 |
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Functional Description
SERIAL BUS OPERATION
Bus Overview
The MPL bus is a simple 2-signal line interface that is
intended to replace wide low voltage CMOS video busses
inside handheld portable devices. The MPL physical layer is
purpose-built for an extremely low power and low EMI data
transmission while requiring the fewest number of signal
lines. No external line components are required, as termina-
tion is provided internal to the MPL receiver. The MPL inter-
face is designed to be used with common 50
lines using
standard materials and connectors. Lines may be microstrip
or stripline construction. Total length of the interconnect is
expected to be less than 0.3 meters. This device is meets
the requirements of the MPL-0 Standard (PHY Layer only).
SERIAL BUS TIMING
Data valid is relative to both edges as shown in
Figure 4
.
Data valid is specified as: Data Valid before Clock, Data
SERIAL BUS PHASES
There are three bus phases on the MPL serial bus. These
are determined by the state of the MC and MD lines. Two of
the bus phases have options. The MPL bus phases are
shown in
Table 1
.
TABLE 1. MPL Bus Phases
Name
WC State
0
A
A
A
MC State
0
0
A
A
MD State
0
0
0
X
Phase Description
Bus is Powered-Off
WC Start Up
MPL Start Up
Data Out (Write)
Pre-Phase
na
O
I (WC)
I (MC)
Post-Phase
I (WC)
I (MC)
A
A or O
OFF (O)
Initialization (I)
WC
MC/MD
Active (A)
Notes on Line State:
0 = no current (off), L = Logic Low, H = Logic High, X = Low or High, A—Active Clock
20091602
FIGURE 4. Master-to-Slave Timing (MC, MDm)
L
www.national.com
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