參數(shù)資料
型號： LM2502
廠商： National Semiconductor Corporation
英文描述： Mobile Pixel Link (MPL) Display Interface Serializer and Deserializer
中文描述： 移動像素鏈路（MPL）的顯示接口串行器和解串
文件頁數(shù)： 4/27頁
文件大小： 1089K
代理商： LM2502
Pin Descriptions
Pin Name
No.
of Pins
I/O, Type
Description
Master (SER)
Slave (DES)
MPL SERIAL BUS PINS
MD[1:0]
MC
V
SSA
CONFIGURATION/PARALLEL BUS PINS
M/S*
1
2
1
IO, MPL
IO, MPL
Ground
MPL Data Line Driver/Receiver
MPL Clock Line Driver
MPL Ground - see Power/Ground Pins
MPL Data Receiver/Line Driver
MPL Clock Receiver
MPL Ground - see Power/Ground Pins
I,
LVCMOS
I,
LVCMOS
Master/Slave* Input,
M/S* = H for Master
Power_Down* Input,
H = Active
L = Power Down Mode
Multi-function Input Zero (0):
If MODE = L (m68 mode), E input pin,
data is latched on E High-to-Low
transition or E may be static High and
Data is latched on CS* Low-to-High edge
If MODE = H (i80 mode), Read Enable
input pin, active low. Read data is driven
when both RD* and CS* are Low.
Multi-function Input One (1):
If Mode = L (m68 mode), Read/Write*
pin, Read High, Write* Low
If Mode = H (i80 mode), Write* enable
input pin, active Low. Write data is
latched on the Low-to-High transition of
either WR* or CS* (which ever occurs
first).
ChipSelect1* – Input
H = Ignored
L = Active
ChipSelect2* – Input
H = Ignored
L = Active
Address/Data – Input
H = Data
L = Address (Command)
Data Bus – Inputs/Outputs
Master/Slave* Input
M/S* = L for Slave
Power_Down* Input,
H = Active
L = Power Down Mode
Multi-function Output Zero (0):
If MODE = L (m68 mode),
E output pin, static High.
If MODE = H (i80 mode),
Read Enable output pin, active Low.
PD*
1
MF0
(E or RD*)
1
IO,
LVCMOS
MF1
(R/W* or
WR*)
1
IO,
LVCMOS
Multi-function Output One (1):
If Mode = L (m68 mode)
Read/Write* pin,
Read High, Write* Low
If Mode = H (i80 mode)
Write* enable output pin, active Low.
CS1*
1
IO,
LVCMOS
ChipSelect1* – Output
H = Ignored
L = Active
ChipSelect2* – Output
H = Ignored
L = Active
Address/Data – Output
H = Data
L = Address (Command)
Data Bus – Outputs/Inputs
CS2*
1
IO,
LVCMOS
A/D (RS or
A0)
1
IO,
LVCMOS
D[15:0]
16
IO,
LVCMOS
O or I,
LVCMOS
INTR
or
CLKDIS*
1
INTR is asserted when the read data is
ready and de-asserted upon a second
CPU Read cycle.
Clock Disable - CLKDIS*:
H = CLK output ON
L = CLK output LOW, allows for the
Slave clock output to be held static if not
used.
Clock Output (Frequency Reference) –
no phase relationship to data – frequency
reference only.
Mode Input Pin
H = i80 Mode,
L = m68 Mode
Clock Divisor Configuration Input Pins –
see
Table 10
CLK
1
IO,
LVCMOS
Clock Input
Mode
1
I,
LVCMOS
Mode Input Pin
H = i80 Mode,
L = m68 Mode
PLL Configuration Input Pins – see
Table
10
PLL_CON
[2:0]
3
I,
LVCMOS
L
www.national.com
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PDF描述
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相關代理商/技術(shù)參數(shù)
參數(shù)描述
LM2502SM 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Mobile Pixel Link (MPL) Display Interface Serializer and Deserializer
LM2502SM/NOPB 功能描述:串行器/解串器 - Serdes RoHS:否 制造商:Texas Instruments 類型:Deserializer 數(shù)據(jù)速率:1.485 Gbit/s 輸入類型:ECL/LVDS 輸出類型:LVCMOS 輸入端數(shù)量:1 輸出端數(shù)量:20 工作電源電壓:2.375 V to 2.625 V 工作溫度范圍:0 C to + 70 C 封裝 / 箱體:TQFP-64
LM2502SMX/NOPB 功能描述:串行器/解串器 - Serdes RoHS:否 制造商:Texas Instruments 類型:Deserializer 數(shù)據(jù)速率:1.485 Gbit/s 輸入類型:ECL/LVDS 輸出類型:LVCMOS 輸入端數(shù)量:1 輸出端數(shù)量:20 工作電源電壓:2.375 V to 2.625 V 工作溫度范圍:0 C to + 70 C 封裝 / 箱體:TQFP-64
LM2502SQ 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Mobile Pixel Link (MPL) Display Interface Serializer and Deserializer
LM2502SQ/NOPB 功能描述:串行器/解串器 - Serdes RoHS:否 制造商:Texas Instruments 類型:Deserializer 數(shù)據(jù)速率:1.485 Gbit/s 輸入類型:ECL/LVDS 輸出類型:LVCMOS 輸入端數(shù)量:1 輸出端數(shù)量:20 工作電源電壓:2.375 V to 2.625 V 工作溫度范圍:0 C to + 70 C 封裝 / 箱體:TQFP-64
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