參數(shù)資料
型號: LM2502SQ
廠商: NATIONAL SEMICONDUCTOR CORP
元件分類: 通用總線功能
英文描述: Mobile Pixel Link (MPL) Display Interface Serializer and Deserializer
中文描述: LINE TRANSCEIVER, QCC40
封裝: 5 X 5 MM, 0.80 MM HEIGHT, 0.40 MM PITCH, LEAD FREE, LLP-40
文件頁數(shù): 18/27頁
文件大小: 1089K
代理商: LM2502SQ
Functional Description
(Continued)
TABLE 6. READ—6800 μP Interface Parameters
(Continued)
Parameter
Recovery Time
INTR Response, (Note 5)
No.
T15
T16
Min
Typ
5
Max
Units
ns
MC Cycles
MasterOUT
MasterOUT
0
For the MOT CPU 68xx mode, the Master accepts data on the CS* Low-to-High transition or the E High-to-Low transition, which
ever come first. The Slave output only uses the CS* pin for data strobe/latch, as the E signal is held constantly High.
CPU MODE—WRITE—i80
TABLE 7. WRITE—80xx μP Interface Parameters
No.
T1
T2
T3
T4
T5
T6
T7
T8
T9
Parameter
Min
5
5
6
Typ
Max
Units
ns
ns
MC Cycles
MC Cycles
MC Cycles
MC Cycles
MC Cycles
MC Cycles
MC Cycles
MasterIN
MasterIN
MasterIN
Master
Slave
SlaveOUT
SlaveOUT
SlaveOUT
SlaveOUT
Data Setup before Write* High
Data Hold after Write* High
Write* Recovery Time, (Note 5)
Master Latency
Slave Latency
Data Valid before Write* High-to-Low
WR* Pulse Width Low
Data Valid before Write* Low-to-High
Data Valid after Write* Low-to-High
5
9
1
3
4
1
20093312
FIGURE 15. WRITE—80xx μP Interface
L
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