PWM Operation
(Continued)
LDO Operation
Connecting the SYNC/MODE pin to SGND sets the LM2608
to Linear mode operation. While in LDO (Low Dropout regu-
lator) mode, the output voltage is regulated by the internal
LDO to supply up to 3mA. This is done by using an internal
pass transistor and an error amplifier to sense the output
voltage and maintain the desired output voltage. During LDO
mode, the PFET and NFET network switch off to reduce
quiescent current.
Operating Mode Selection
(SYNC/MODE Pin)
The SYNC/MODE digital input pin is used to select between
PWM and LDO operating modes. Set SYNC/MODE high
(above 1.3V) for 600kHz PWM operation. Set SYNC/MODE
low (below 0.4V) to select LDO mode to reduced current
consumption when the system is in standby. The LM2608
has an over-voltage protection feature that may activate if
the device is left in PWM mode under low-load conditions to
prevent the output voltage from rising too high. See
Over-
voltage Protection
, for more information.
Select modes with the SYNC/MODE pin using a signal with
a slew rate faster than 5V/100μs. Use a comparator Schmitt
trigger or logic gate to drive the SYNC/MODE pin. Do not
leave the pin floating or allow it to linger between logic levels.
These measures will prevent output voltage errors that could
otherwise occur in response to an indeterminate logic state.
Frequency Synchronization
(SYNC/MODE Pin)
The SYNC/MODE input can also be used for frequency
synchronization. To synchronize the LM2608 to an external
clock, supply a digital signal to the SYNC/MODE pin with a
voltage swing exceeding 0.4V to 1.3V. During synchroniza-
tion, the LM2608 initiates cycles on the rising edge of the
clock. When synchronized to an external clock, it operates in
PWM mode. The device can synchronize to an external
clock over frequencies from 500kHz to 1MHz.
Use the following waveform and duty-cycle guidelines when
applying an external clock to the SYNC/MODE pin. The duty
cycle can be between 30% and 70%. Clock under/overshoot
should be less than 100mV below GND or above VDD.
When applying noisy clock signals, especially sharp edged
signals from a long cable during evaluation, terminate the
cable at its characteristic impedance; add an RC filter to the
SYNC pin, if necessary, to soften the slew rate and over/
undershoot. Note that sharp edged signals from a pulse or
function generator can develop under/overshoot as high as
10V at the end of an improperly terminated cable.
Overvoltage Protection
The LM2608 has an over-voltage comparator that prevents
the output voltage from rising too high when the device is left
in PWM mode under low-load conditions. Otherwise, the
output voltage could rise out of regulation from the minimum
energy transferred per cycle due to the 200nS minimum
on-time of the PFET switch while in PWM mode. When the
output voltage rises by 45mV over its regulation threshold,
the OVP comparator inhibits PWM operation to skip pulses
until the output voltage returns to the regulation threshold. In
over voltage protection, output voltage and ripple increase
slightly.
Shutdown Mode
Setting the EN input low, to SGND, places the LM2608 in a
0.02μA (typ) shutdown mode. During shutdown, the PFET
switch, NFET synchronous rectifier, reference, control and
bias of the LM2608 are turned off. Setting EN high to VDD
enables normal operation. While turning on, soft start is
activated. EN is a Schmitt trigger digital input with thresholds
that are independent of the input voltage at VDD.
EN must be set low to turn off the LM2608 during undervolt-
age conditions when the supply is less than the 2.8V mini-
mum operating voltage. The LM2608 is designed for mobile
phones and similar applications where power sequencing is
determined by the system controller and internal UVLO (Un-
der Voltage LockOut) circuitry is unnecessary. The LM2608
PWM Mode Switching Waveform
20036624
FIGURE 3.
L
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