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參數(shù)資料
| 型號： | LM2651 |
| 文件頁數(shù)： | 4/11頁 |
| 文件大?。?/td> | 215K |
| 代理商： | LM2651 |
Electrical Characteristics
(Continued)
V
= 15V, V
SLEEP LOGIC
= 0V and V
SD
= 0V unless superseded under
Conditions
. Typicals and limits appearing in plain
type apply for T
J
boldface
type apply over the full junction temperature range shown under
Operating Ratings
.
Symbol
Parameter
Conditions
D
MIN
Minimum Duty Cycle
V
FB
= V
REF
+50 mV,
F
OSC
Not Adjusted
V
DD
Internal Rail Voltage
I
VDD
= 1 mA
Typ
(Note 5)
2.8
Limit
(Note 6)
Units
%
%(min)
V
V(min)
V(max)
V
V(min)
μA
μA(max)
mV
mV(min)
mV(max)
V(max)
V(min)
V(max)
V(min)
V(max)
V(min)
C
5
4.0
3.6/
3.4
4.2/
4.3
V
BOOT
Bootstrap Regulator Voltage
(VRegH)
Soft Start Current
I
BOOT
= 1 mA
7.5
6.5/
6.0
I
SS
10
13.5/
20.0
V
HYST
Hysteresis of the Sleep
Comparator (C2Figure 2)
V
SLEEPLOGIC
= 3V
30
10
50
0.95
2.10
0.9
2.0
0.50
1.45
V
IL
of SD
V
IH
of SD
V
IL
of SLEEP LOGIC
V
IH
of SLEEP LOGIC
V
IL
of SYNC
V
IH
of SYNC
T
J
for Thermal Shutdown
T
SD
170
Note 1:
Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions under which the device operates
correctly. Operating ratings do not imply guaranteed performance limits. For guaranteed performance limits and associated test conditions, see the Electrical
Characteristics.
Note 2:
This rating is calculated using the formula P
DCmax
= (T
Jmax
T
A
) /
θ
JA
, where P
DCmax
is the absolute maximum power dissipation, T
Jmax
is the maximum
junction temperature, and
θ
JA
is the junction ot ambient thermal resistance of the package. The P
DCmax
rating of 1.28W results from substituting 170C, 70C and
78C/W for T
Jmax
, T
A
and
θ
JA
respectively. A
θ
JA
of 78C represents the worst condition of no heat sinking of the M24B small-outline package. Heat sinking allows
the safe dissipation of more power. See Application Notes on thermal management. The LM2650 actively limits its junction temperature to about 170C.
Note 3:
For detailed information on soldering plastic small-outline packages, refer to the Packaging Databook published by National Semiconductor Corporation.
Note 4:
ESD is applied using the human-body model, a 100pF capacitor discharged through a 1.5k
resistor.
Note 5:
A typical is the center of characterization data taken at T
A
= T
J
= 25C.
Note 6:
All limits are guaranteed. The guarantee is backed with 100% testing at T
A
= T
J
= 125C and statistical correlation for room temperature and cold limits.
Note 7:
V
REF
is measured at SLEEP OUT ADJ.
Note 8:
Quiescent current is the total current flowing into the P
VIN
and V
IN
pins. I
Q
includes the current used to drive the gates of the two NMOS power FETs at the
nominal switching frequency. I
QS
includes no such current.
Note 9:
Pulling 100μA out of FREQ ADJ simulates adjusting the oscillator frequency with a 12.5 k
resistor connected from FREQ ADJ to GND. The sleep mode
cannot be used at switching frequencies above 250 kHz.
L
www.national.com
4
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