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參數(shù)資料
| 型號(hào)： | LM2716MTX-ADJ |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | Dual (Step-up and Step-down) PWM DC/DC Converter |
| 中文描述： | DUAL SWITCHING CONTROLLER, 700 kHz SWITCHING FREQ-MAX, PDSO24 |
| 封裝： | TSSOP-24 |
| 文件頁(yè)數(shù)： | 13/17頁(yè) |
| 文件大?。?/td> | 563K |
| 代理商： | LM2716MTX-ADJ |
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Boost Operation
(Continued)
Resistance, denoted R
ESR
) capacitors be used such as
ceramic, polymer electrolytic, or low ESR tantalum. Higher
ESR capacitors may be used but will require more compen-
sation which will be explained later on in the section. The
ESR is also important because it determines the peak to
peak output voltage ripple according to the approximate
equation:
V
OUT
)
2
i
L
R
ESR
(in Volts)
A minimum value of 10μF is recommended and may be
increased to a larger value.After choosing the output capaci-
tor you can determine a pole-zero pair introduced into the
control loop by the following equations:
Where R
is the minimum load resistance corresponding to
the maximum load current. The zero created by the ESR of
the output capacitor is generally very high frequency if the
ESR is small. If low ESR capacitors are used it can be
neglected. If higher ESR capacitors are used see the
High
Output Capacitor ESR Compensation
section.
RIGHT HALF PLANE ZERO
A current mode control boost regulator has an inherent right
half plane zero (RHP zero). This zero has the effect of a zero
in the gain plot, causing an imposed +20dB/decade on the
rolloff, but has the effect of a pole in the phase, subtracting
another 90 in the phase plot. This can cause undesirable
effects if the control loop is influenced by this zero. To ensure
the RHP zero does not cause instability issues, the control
loop should be designed to have a bandwidth of less than
1
2
the frequency of the RHP zero. This zero occurs at a fre-
quency of:
where I
LOAD
is the maximum load current.
SELECTING THE COMPENSATION COMPONENTS
The first step in selecting the compensation components
R
C2
and C
C2
is to set a dominant low frequency pole in the
control loop. Simply choose values for R
C2
and C
C2
within
the ranges given in the
Introduction to Compensation
section
to set this pole in the area of 10Hz to 500Hz. The frequency
of the pole created is determined by the equation:
where R
is the output impedance of the error amplifier,
approximately 850k
. Since R
C2
is generally much less than
R
O
, it does not have much effect on the above equation and
can be neglected until a value is chosen to set the zero f
ZC
.
f
ZC
is created to cancel out the pole created by the output
capacitor, f
P1
. The output capacitor pole will shift with differ-
ent load currents as shown by the equation, so setting the
zero is not exact. Determine the range of f
P1
over the ex-
pected loads and then set the zero f
to a point approxi-
mately in the middle. The frequency of this zero is deter-
mined by:
Now R
can be chosen with the selected value for C
.
Check to make sure that the pole f
is still in the 10Hz to
500Hz range, change each value slightly if needed to ensure
both component values are in the recommended range.After
checking the design at the end of this section, these values
can be changed a little more to optimize performance if
desired. This is best done in the lab on a bench, checking the
load step response with different values until the ringing and
overshoot on the output voltage at the edge of the load steps
is minimal. This should produce a stable, high performance
circuit. For improved transient response, higher values of
R
should be chosen. This will improve the overall band-
width which makes the regulator respond more quickly to
transients. If more detail is required, or the most optimal
performance is desired, refer to a more in depth discussion
of compensating current mode DC/DC switching regulators.
HIGH OUTPUT CAPACITOR ESR COMPENSATION
When using an output capacitor with a high ESR value, or
just to improve the overall phase margin of the control loop,
another pole may be introduced to cancel the zero created
by the ESR. This is accomplished by adding another capaci-
tor, C
C4
, directly from the compensation pin V
C2
to ground, in
parallel with the series combination of R
C2
and C
C2
. The
pole should be placed at the same frequency as f
Z1
, the ESR
zero. The equation for this pole follows:
To ensure this equation is valid, and that C
C4
can be used
without negatively impacting the effects of R
C2
and C
C2
, f
PC4
must be greater than 10f
ZC
.
CHECKING THE DESIGN
The final step is to check the design. This is to ensure a
bandwidth of
1
2
or less of the frequency of the RHP zero.
This is done by calculating the open-loop DC gain,A
.After
this value is known, you can calculate the crossover visually
by placing a 20dB/decade slope at each pole, and a +20dB/
decade slope for each zero. The point at which the gain plot
crosses unity gain, or 0dB, is the crossover frequency. If the
crossover frequency is less than
1
2
the RHP zero, the phase
margin should be high enough for stability. The phase mar-
gin can also be improved by adding C
C4
as discussed earlier
in the section. The equation for A
DC
is given below with
additional equations required for the calculation:
L
www.national.com
13
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| LM2716MT-ADJ | Dual (Step-up and Step-down) PWM DC/DC Converter |
| LM2716 | Dual (Step-up and Step-down) PWM DC/DC Converter |
| LM2717 | Dual Step-down DC/DC Converter |
| LM2717MT | Dual Step-down DC/DC Converter |
| LM2717MTX | Dual Step-down DC/DC Converter |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LM2717 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Dual Step-down DC/DC Converter |
| LM2717_08 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Dual Step-Down DC/DC Converter |
| LM2717-ADJ | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Dual Step-Down DC/DC Converter |
| LM2717-ADJ_08 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Dual Step-Down DC/DC Converter |
| LM2717MT | 功能描述:DC/DC 開關(guān)控制器 RoHS:否 制造商:Texas Instruments 輸入電壓:6 V to 100 V 開關(guān)頻率: 輸出電壓:1.215 V to 80 V 輸出電流:3.5 A 輸出端數(shù)量:1 最大工作溫度:+ 125 C 安裝風(fēng)格: 封裝 / 箱體:CPAK |
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