參數(shù)資料
型號: LM2722M
廠商: NATIONAL SEMICONDUCTOR CORP
元件分類: 功率晶體管
英文描述: High Speed Synchronous/Asynchronous MOSFET Driver
中文描述: 3.2 A HALF BRDG BASED MOSFET DRIVER, PDSO8
封裝: PLASTIC, SO-8
文件頁數(shù): 7/8頁
文件大?。?/td> 162K
代理商: LM2722M
Typical Waveforms
Application Information
Minimum Pulse Width
In order for the shoot-through prevention circuitry in the
LM2722 to work properly, the pulses into the PWM_IN pin
must be longer than 55ns. The internal logic waits until the
first FET is off plus 20ns before turning on the opposite FET.
If, after a falling edge, a rising edge occurs sooner than the
specified time, t
, the IC may intermittently fail to turn on
the top gate when the bottom gate is off. As the rising edge
occurs sooner and sooner, the driver may start to ignore the
pulse and produce no output. This condition results in the
PWM_IN pin in a high state and neither FET turned on. To
get out of this state, the PWM_IN pin must see a low signal
for greater than 55ns, before the rising edge.
This will also assure that the gate drive bias voltage has
been restored by forcing the top FET source and C
boot
to
ground first. Then the internal circuitry is reset and normal
operation will resume.
Conversely, if, after a rising edge, a falling edge occurs
sooner than the specified miniumum pulse width, t
on_min
, the
IC may intermittently fail to turn on the bottom FET. As the
falling edge occurs sooner and sooner, the driver will start to
ignore the pulse and produce no output. This will result in the
t
inductor current taking a path through a diode provided
for non-synchronous operation. The circuit will resume syn-
chronous operation when the rising PWM pulses exceed
55ns in duration.
High Input Voltages or High Output Currents
At input voltages above twice the output voltage and at
higher power levels, the designer may find snubber networks
and gate drive limiting useful in reducing EMI and preventing
injurious transients. A small resistor, 1
to 5
, between the
driver outputs and the MOSFET gates will slightly increase
the rise time and fall time of the output stage and reduce
switching noise. The trade-off is 1% to 2% in efficiency.
A series R-C snubber across in parallel with the bottom FET
can also be used to reduce ringing. Values of 10nF and 10
to 100
are a good starting point.
20028913
FIGURE 1. Switching Waveforms of Test Circuit
20028914
FIGURE 2. When Input Goes High
20028915
FIGURE 3. When Input Goes Low
20028916
FIGURE 4. Minimum Positive Pulse
L
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