參數(shù)資料
型號(hào): LM2750LDX-ADJ
廠商: NATIONAL SEMICONDUCTOR CORP
元件分類: 穩(wěn)壓器
英文描述: Low Noise, 5.0V Regulated Switched Capacitor Voltage Converter
中文描述: SWITCHED CAPACITOR REGULATOR, PDSO10
封裝: 3 X 3 MM, LLP-10
文件頁(yè)數(shù): 4/15頁(yè)
文件大?。?/td> 370K
代理商: LM2750LDX-ADJ
Electrical Characteristics
Typical values and limits in standard typeface apply for T
J
= 25
o
C. Limits in boldface type apply over the operating junction
temperature range. Unless otherwise specified: 2.9V
V
IN
5.6V, V
OUT
= 5.0V (LM2750-ADJ), V(SD) = V
IN
, C
FLY
= 1μF, C
IN
= 2 x 1μF, C
OUT
= 2 x 1μF (Note 8).
Symbol
Parameter
Conditions
Capacitor Requirements
Required Input
Capacitance(Note 12)
60mA
I
OUT
120mA
C
OUT
Required Output
Capacitance(Note 12)
60mA
I
OUT
120mA
(Notes 2, 7) (Continued)
Min
Typ
Max
Units
C
IN
I
OUT
60mA
1.0
2.0
1.0
2.0
μF
I
OUT
60mA
μF
Note 1:
Absolute Maximum Ratings indicate limits beyond which damage to the component may occur. Operating Ratings are conditions under which operation of
the device is guaranteed. Operating Ratings do not imply guaranteed performance limits. For guaranteed performance limits and associated test conditions, see the
Electrical Characteristics tables.
Note 2:
All voltages are with respect to the potential at the GND pin.
Note 3:
Thermal shutdown circuitry protects the device from permanent damage. Thermal shutdown engages at T
J
=150C (typ.) and disengages at T
J
=135C (typ.).
Note 4:
The Human body model is a 100 pF capacitor discharged through a 1.5 k
resistor into each pin. MIL-STD-883 3015.7. The machine model is a 200pF
capacitor discharged directly into each pin.
Note 5:
Maximum ambient temperature (T
A-MAX
) is dependent on the maximum operating junction temperature (T
J-MAX-OP
= 125
o
C), the maximum power
dissipation of the device in the application (P
), and the junction-to ambient thermal resistance of the part/package in the application (
θ
), as given by the
following equation: T
A-MAX
= T
- (
θ
JA
x P
D-MAX
). Maximum power dissipation of the LM2750 in a given application can be approximated using the following
equation: P
= (V
x I
) - (V
) = [V
x ((2 x I
) + 5mA)] - (V
x I
). In this equation, V
IN-MAX
, I
IN-MAX
, and
I
OUT-MAX
are the maximum voltage/current of the specific application, and not necessarily the maximum rating of the LM2750.
The maximum ambient temperature rating of 85
o
C is determined under the following application conditions:
θ
= 55
o
C/W, P
= 727mW (achieved when
V
= 5.5V and I
= 115mA, for example). Maximum ambient temperature must be derated by 1.1
o
C for every increase in internal power dissipation of
20mW above 727mW (again assuming that
θ
= 55
o
C/W in the application). For more information on these topics, please refer to
Application Note 1187: Leadless
Leadframe Package (LLP)
and the
Power Efficiency and Power Dissipation
section of this datasheet.
Note 6:
Junction-to-ambient thermal resistance (
θ
) is taken from a thermal modeling result, performed under the conditions and guidelines set forth in the JEDEC
standard JESD51-7. The test board is a 4 layer FR-4 board measuring 102mm x 76mm x 1.6mm with a 2 x 1 array of thermal vias. The ground plane on the board
is 50mm x 50mm. Thickness of copper layers are 36μm/18μm /18μm/36μm (1.5oz/1oz/1oz/1.5oz). Ambient temperature in simulation is 22C, still air. Power
dissipation is 1W.
The value of
θ
JA
of the LM2750 in LLP-10 could fall in a range as wide as 50
o
C/W to 150
o
C/W (if not wider), depending on PCB material, layout, and environmental
conditions. In applications where high maximum power dissipation exists (high V
IN
, high I
OUT
), special care must be paid to thermal dissipation issues. For more
information on these topics, please refer to
Application Note 1187: Leadless Leadframe Package (LLP)
and the
Layout Recommendations
section of this
datasheet.
Note 7:
Min and Max limits are guaranteed by design, test, or statistical analysis. Typical numbers are not guaranteed, but do represent the most likely norm.
Note 8:
C
FLY
, C
IN
, and C
OUT
: Low-ESR Surface-Mount Ceramic Capacitors (MLCCs) used in setting electrical characteristics
Note 9:
Turn-on time is measured from when SD signal is pulled high until the output voltage crosses 90% of its final value.
Note 10:
Efficiency is measured versus V
IN
, with V
IN
being swept in small increments from 3.0V to 4.2V. The average is calculated from these measurements
results. Weighting to account for battery voltage discharge characteristics (V
BAT
vs. Time) is not done in computing the average.
Note 11:
SD Input Current (I
IH
) is due to a 200k
(typ.) pull-down resistor connected internally between the SD pin and GND.
Note 12:
Limit is the minimum required output capacitance to ensure proper operation. This electrical specification is guaranteed by design.
L
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