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參數(shù)資料
| 型號(hào)： | LM2926 |
| 廠商： | National Semiconductor Corporation |
| 元件分類： | 基準(zhǔn)電壓源/電流源 |
| 英文描述： | Cap-Free, NMOS, 150mA Low Dropout Regulator with Reverse Current Protection |
| 中文描述： | 無(wú)電容，NMOS管，150mA的低壓差穩(wěn)壓器的反向電流保護(hù) |
| 文件頁(yè)數(shù)： | 5/10頁(yè) |
| 文件大小： | 404K |
| 代理商： | LM2926 |
Typical Performance Characteristics
(Continued)
Typical Circuit Waveforms
Applications Information
EXTERNAL CAPACITORS
The LM2926/7 output capacitor is required for stability. With-
out it, the regulator output will oscillate at amplitudes as high
as several volts peak-to-peak at frequencies up to 500 kHz.
Although 10 μF is the minimum recommended value, the ac-
tual size and type may vary depending upon the application
load and temperature range. Capacitor equivalent series re-
sistance (ESR) also affects stability. The region of stable op-
eration is shown in the
Typical Performance Characteris-
tics
(Output Capacitor ESR curve).
Output capacitors can be increased in size to any desired
value above 10 μF. One possible purpose of this would be to
maintain the output voltage during brief conditions of input
transients that might be characteristic of a particular system.
Capacitors must also be rated at all ambient temperatures
expected in the system. Many aluminum electrolytics freeze
at temperatures below 30C, reducing their effective ca-
pacitance to zero. To maintain regulator stability down to
40C, capacitors rated at that temperature (such as tantal-
ums) must be used.
DELAYED RESET
The delayed reset output is designed to hold a microproces-
sor in a reset state on system power-up for a programmable
time interval to allow the system clock and other powered cir-
cuitry to stabilize.Afull reset interval is also generated when-
ever the output voltage falls out of regulation. The circuit is
tripped whenever the output voltage of the regulator is out of
regulation by the Reset Threshold value. This can be caused
by low input voltages, over current conditions, over-voltage
shutdown, thermal shutdown, and by both power-up and
power-down sequences. When the reset circuit detects one
of these conditions, the delay capacitor is discharged by an
SCR and held in a discharged state by a saturated NPN
switch. As long as the delay capacitor is held low, the reset
output is also held low. Because of the action of the SCR, the
reset output cannot glitch on noise or transient fault condi-
tions. A full reset pulse is obtained for any fault condition that
trips the reset circuit.
When the output regains regulation, the SCR is switched off
and a small current (I
DELAY
= 2 μA) begins charging the de-
Reset Delay
DS010759-29
Reset Delay
DS010759-30
DS010759-5
5
www.national.com
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