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Output Capacitor Selection
(Continued)
input voltage is the highest and when the present switching
cycle has just finished. The corresponding minimum capaci-
tance is calculated as follows:
(8)
Notice it is already assumed the total ESR, R
esr
, is no
greater than R
esr_max
, otherwise the term under the square
root will be a negative value. Also, it is assumed that L has
already been selected, therefore the minimum L value
should be calculated before C
MIN
and after R
esr
(see Induc-
tor Selection below). Example: R
esr
= 20m
, V
OUT
= 5V,
V
TRANS
= 160mV,
I
TRANS
= 3A, L = 8μH
(9)
Generally speaking, C
decreases with decreasing R
,
I
, and L, but with increasing V
and
V
. The
output capacitance can therefore be chosen to be slightly
larger than the calculated value so that it is more easily
available. Here we would likely be fine choosing 220 μF.
Inductor Selection
The size of the output inductor can be determined from the
desired output ripple voltage,
V
OUT
, and the impedance of
the output capacitors at the switching frequency. The equa-
tion to determine the minimum inductance value is as fol-
lows:
(10)
In the above equation, R
is used in place of the imped-
ance of the output capacitors. This is because in most cases,
the impedance of the output capacitors at the switching
frequency is very close to R
. In the case of ceramic
capacitors, replace R
esr
with the true impedance.
Example:
V
IN_MAX
= 36V, V
OUT
= 5.0V,
V
OUT
= 40 mV, R
esr
= 20 m
, f
SW
(11)
The actual selection process usually involves several itera-
tions of all of the above steps, from ripple voltage selection,
to capacitor selection, to inductance calculations. Both the
highest and the lowest input and output voltages and load
transient requirements should be considered. If an induc-
tance value larger than L
MIN
is selected, make sure that the
C
MIN
requirement is not violated.
Priority should be given to parameters that are not flexible or
more costly. For example, if there are very few types of
capacitors to choose from, it may be a good idea to adjust
the inductance value so that a requirement of 3.2 capacitors
can be reduced to 3 capacitors.
Since inductor ripple current is often the criterion for select-
ing an output inductor, it is a good idea to double-check this
value. The equation is:
(12)
Where D is the duty cycle, defined by V
OUT
/V
IN
.
Also important is the ripple current, which is defined by
I
L
/I
NOM
., where I
NOM
is the nominal output current. Generally
speaking, a ripple content of less than 50% is ok. Larger
ripple content causes excessive losses in the inductor.
Example:
V
IN
= 12V, V
OUT
= 5.0V, f
SW
= 300 kHz, L = 8 μH
(13)
Given a maximum load current of 5A, the ripple content is
1.2A / 5A = 24%. When choosing an inductor, the saturation
current should be higher than the maximum peak inductor
current and the RMS current rating should be higher than the
maximum load current.
Input Capacitor Selection
The input capacitor must be selected such that it can handle
both the maximum ripple RMS current at highest ambient
temperature and the maximum input voltage. The equation
for the RMS current through the input capacitor is then
(14)
Where I
MAX
is maximum load current and D is the duty cycle.
Example: I
MAX
= 5A and D = 0.42
(15)
The function D(1-D) has a maxima at D = 0.5. This duty cycle
corresponds to the maximum RMS input current that may be
used as a worst case in selecting an input capacitor. Input
capacitors must meet the minimum requirements of voltage
and ripple current capacity. The size of the capacitor should
then be selected based on hold up time requirements. Bench
testing for individual applications is still the best way to
determine a reliable input capacitor value. The input capaci-
tor should always be placed as close as possible to the
current sense resistor or the drain of the top FET.
MOSFET Selection
BOTTOM FET SELECTION
During normal operation, the bottom FET is switching at
almost zero voltage and therefore only conduction losses
are present in the bottom FET. This makes the on resistance
(R
) the most important parameter when selecting the
bottom FET; the lower the on resistance, the lower the power
loss. The bottom FETs’ power losses peak at the maximum
L
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