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參數(shù)資料
| 型號： | LM339 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Quad Differencial Comparators(四電壓比較器) |
| 中文描述： | 四差動比較（四電壓比較器） |
| 文件頁數(shù)： | 6/10頁 |
| 文件大?。?/td> | 75K |
| 代理商： | LM339 |
Philips Semiconductors
Product specification
LM139/239/239A/339/339A/
LM2901/MC3302
Quad voltage comparator
1995 Nov 27
6
DC AND AC ELECTRICAL CHARACTERISTICS
V+=5V
DC
, LM139: –55
°
C
≤
T
A
≤
125
°
C; LM239/239A: –25
°
C
≤
T
A
≤
85
°
C; LM339/339A: 0
°
C
≤
T
A
≤
70
°
C; LM2901: –40
°
C
≤
T
A
≤
125
°
C,
MC3302: –40
°
C
≤
T
A
≤
85
°
C, unless otherwise specified.
SYMBOL
PARAMETER
TEST CONDITIONS
LM2901
Typ
±
2.0
±
9
MC3302
Typ
±
3.0
UNIT
Min
Max
±
7.0
±
15
V+–1.5
V+–2.0
Min
Max
±
20
±
40
V+–1.5
V+–2.0
V
OS
Input offset voltage
2
T
A
=25
°
C
Over temp.
T
A
=25
°
C
Over temp.
Keep all
V
INs
≥
0V
DC
(or V– if need)
I
IN(+)
or I
IN(–)
with output in
linear range
T
A
=25
°
C
Over temp.
I
IN(+)
–I
IN(–)
T
A
=25
°
C
Over temp.
V
IN(–)
≥
1V
DC
, V
IN
(+)=0,
V
O
≤
1.5V
DC
,
T
A
=25
°
C
V
IN(+)
≥
1V
DC
, V
IN
(–)=0
V
O
=5V
DC
,
T
A
=25
°
C
V
O
=30V
DC
,
over temp.
R
L
=
∞
on all comparators,
T
A
=25
°
C
R
L
=
∞
on all comparators, V+=30V
R
L
≥
15k
,
V+=15V
DC
V
IN(–)
≥
1V
DC
, V
IN(+)
=0,
I
SINK
≤
4mA
T
A
=25
°
C
Over temp.
V
IN
=TTL logic swing, V
REF
=1.4V
DC
,
V
RL
=5V
DC
, R
L
=5.1k
, T
A
=25
°
C
V
RL
=5V
DC
, R
L
=5.1k
,
T
A
=25
°
C
mV
mV
V
CM
Input common–mode voltage
range
3
0
0
0
0
V
V
IDR
Differential input voltage
1
V+
V+
V
I
BIAS
Input bias current
4
25
200
250
500
25
500
1000
nA
nA
I
OS
Input offset current
±
5
±
50
16
±
50
±
200
±
5
±
100
±
300
nA
nA
I
OL
Output sink current
6.0
6
16
mA
Output leakage current
0.1
0.1
nA
1.0
1.0
1.8
μ
A
mA
.8
I
CC
Supply current
0.8
1.0
2.0
2.5
mA
A
V
Voltage gain
25
100
2
100
V/mV
V
OL
Saturation voltage
400
400
700
150
400
700
mV
mV
t
LSR
Large–signal response time
300
300
ns
t
R
Response time
5
1.3
1.3
μ
s
NOTES:
1. Positive excursions of input voltage may exceed the power supply level by 17V. As long as the other voltage remains within the
common-mode range, the comparator will provide a proper output state. The low input voltage state must not be less than –0.3V
DC
(or
0.3V
below the magnitude of the negative power supply, if used).
2. At output switch point, V
O
≈
1.4V
DC
, R
S
=0
with V+ from 5V
DC
to 30V
DC
; and over the full input common–mode range (0V
DC
to
V+ – 1.5V
DC
). Inputs of unused comparators should be grounded.
3. The input common–mode voltage or either input signal voltage should not be allowed to go negative by more than 0.3V. The upper end of
the common–mode voltage range is V+ – 1.5V, but either or both inputs can go to 30V
DC
without damage.
4. The direction of the input current is out of the IC due to the PNP input stage. This current is essentially constant, independent of the state of
the output so no loading change exists on the reference or input lines.
5. The response time specified is for a 100mV input step with a 5mV overdrive. For larger overdrive signals, 300ns can be obtained (see typical
performance characteristics section).
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