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參數(shù)資料
| 型號： | LM3411N-5.0 |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 基準(zhǔn)電壓源/電流源 |
| 英文描述： | IC-VOLTAGE REGULATOR 5V |
| 中文描述： | THREE TERM VOLTAGE REFERENCE, PDIP8 |
| 封裝： | DIP-8 |
| 文件頁數(shù)： | 4/13頁 |
| 文件大?。?/td> | 350K |
| 代理商： | LM3411N-5.0 |
LM3411-5.0 Electrical Characteristics
Specifications with standard type face are for T
= 25C, and those with
boldface type
apply over
full Operating Tempera-
ture Range
. Unless otherwise specified, V(IN) = V
REG
, V
OUT
= 1.5V.
Symbol
Parameter
Conditions
Typical
(Note 4)
LM3411A-5.0
Limit
(Note 5)
LM3411-5.0
Limit
(Note 5)
Units
(Limits)
V
REG
Regulation Voltage
I
OUT
= 5 mA
5
V
5.025/
5.050
4.975/
4.950
±
0.5/
±
1
5.050/
5.100
4.950/
4.900
±
1/
±
2
V(max)
V(min)
%(max)
Regulation Voltage
Tolerance
Quiescent Current
I
OUT
= 5 mA
I
q
I
OUT
= 5 mA
85
μA
110/
115
125/
150
μA(max)
mA/mV
mA/mV(min)
mA/mV
mA/mV(min)
V/V
V/V(min)
V/V
V/V(min)
V
V(max)
μA
μA(max)
k
k
(max)
k
(min)
μV
RMS
G
m
Transconductance
I
OUT
/
V
REG
20 μA
≤
I
OUT
≤
1 mA
3.3
1.5/
0.75
1.0/
0.5
1 mA
≤
I
OUT
≤
15 mA
6.0
3.3/
2.0
2.5/
1.7
A
V
Voltage Gain
V
OUT
/
V
REG
1V
≤
V
OUT
≤
V
REG
1.2V
(1.3)
R
L
= 250
(Note 6)
1V
≤
V
OUT
≤
V
REG
1.2V
(1.3)
R
L
= 2 k
V(IN) = V
REG
+100 mV
I
OUT
= 15 mA
V(IN) = V
REG
100 mV
V
OUT
= 0V
1000
750/
350
650/
300
3500
1500/
900
1000/
700
V
SAT
Output Saturation
(Note 7)
Output Leakage
Current
Internal Feedback
Resistor (Note 8)
1.0
1.2/
1.3
1.2/
1.3
I
L
0.1
0.5/
1.0
0.5/
1.0
R
f
94
118
70
118
70
E
n
Output Noise
Voltage
I
OUT
= 1 mA, 10 Hz
≤
f
≤
10 kHz
80
Note 1:
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is in-
tended to be functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The
guaranteed specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed
test conditions.
Note 2:
The maximum power dissipation must be derated at elevated temperatures and is dictated by T
(maximum junction temperature),
θ
JA
(junction to am-
bient thermal resistance), and T
(ambient temperature). The maximum allowable power dissipation at any temperature is (P
= T
T
)/
θ
or the number
given in the Absolute Maximum Ratings, whichever is lower. The typical thermal resistance (
θ
JA
) when soldered to a printed circuit board is approximately 306C/W
for the M5 package.
Note 3:
The human body model is a 100 pF capacitor discharged through a 1.5 k
resistor into each pin.
Note 4:
Typical numbers are at 25C and represent the most likely parametric norm.
Note 5:
Limits are 100% production tested at 25C. Limits over the operating temperature range are guaranteed through correlation using Statistical Quality Control
(SQC) methods. The limits are used to calculate National’s Averaging Outgoing Level (AOQL).
Note 6:
Actual test is done using equivalent current sink instead of a resistor load.
Note 7:
V
SAT
= V(IN) V
OUT
, when the voltage at the IN pin is forced 100 mV above the nominal regulating voltage (V
REG
).
Note 8:
See Applications and Curves sections for information on this resistor.
L
www.national.com
4
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