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參數(shù)資料
| 型號： | LM4546 |
| 廠商： | National Semiconductor Corporation |
| 元件分類： | Codec |
| 英文描述： | AC ’97 Rev 2 Codec with Sample Rate Conversion and National 3D Sound |
| 中文描述： | 交流\u0026#39;97 Rev 2的編解碼器的采樣率轉(zhuǎn)換和國家3D聲音 |
| 文件頁數(shù)： | 3/18頁 |
| 文件大小： | 308K |
| 代理商： | LM4546 |
Electrical Characteristics
(Notes 1, 3) (Continued)
The following specifications apply for AV
= 5V, DV
= 5V, Fs = 48kHz, single codec configuration, unless otherwise noted.
Limits apply for T
A
= 25C. The reference for 0dB is 1Vrms unless otherwise specified.
Symbol
Parameter
Conditions
LM4546
Units
(Limits)
Typical
(Note 7)
Limit
(Note 8)
Analog to Digital Converters
Dynamic Range (Note 2)
Frequency Response
Digital to Analog Converters
Resolution
Dynamic Range (Note 2)
THD
Total Harmonic Distortion
Frequency Response
Group Delay (Note 2)
Out of Band Energy
Stop Band Rejection
D
T
Discrete Tones
Digital I/O
(Note 2)
-60dB Input THD+N, A-Weighted
-1dB Bandwidth
90
20
86
dB (min)
kHz
18
89
0.01
20 - 21k
Bits
-60dB Input THD+N, A-Weighted
V
IN
= -3dB, f=1kHz, R
L
= 10k
85
dB (min)
%
Hz
mS (max)
dB
dB
dB
2
-40
70
-96
V
IL
Low level input voltage
0.30 x
DVDD
0.40 x
DVDD
0.50 x
DVDD
0.20 x
DVDD
±
10
±
10
V (max)
V
HI
High level input voltage
V (min)
V
OH
High level output voltage
V (min)
V
OL
Low level output voltage
V (max)
I
L
I
L
I
DR
Digital Timing Specifications
(Note 2)
F
BC
BIT_CLK frequency
T
BCP
BIT_CLK period
Input Leakage Current
Tri state Leakage Current
Output drive current
AC Link inputs
High impedance AC Link outputs
AC Link outputs
μA
μA
mA
5
12.288
81.4
MHz
nS
T
CH
BIT_CLK high
Variation of BIT_CLK period from 50%
duty cycle
±
20
% (max)
F
SYNC
T
SP
T
SH
T
SL
SYNC frequency
SYNC period
SYNC high pulse width
SYNC low pulse width
48
20.8
1.3
19.5
kHz
μS
μS
μS
T
SETUP
Setup Time
SDATA_IN, SDATA_OUT to falling
edge of BIT_CLK
Hold time of SDATA_IN, SDATA_OUT
from falling edge of BIT_CLK
BIT_CLK, SYNC, SDATA_IN or
SDATA_OUT
BIT_CLK, SYNC, SDATA_IN or
SDATA_OUT
For cold reset
15
nS (min)
T
HOLD
Hold Time
5
nS (min)
T
RISE
Rise Time
6
nS (max)
T
FALL
Fall Time
6
nS (max)
T
RST_LOW
RESET# active low pulse width
RESET# inactive to BIT_CLK start
up
SYNC active high pulse width
SYNC inactive to BIT_CLK start up
Setup to trailing edge of RESET#
1.0
μS (min)
T
RST2CLK
For cold reset
162.8
nS (min)
T
SH
T
SYNC2CLK
T
SU2RST
For warm reset
For warm reset
For ATE Test Mode
1.3
μS
162.8
15
nS (min)
nS (min)
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LM4546_09 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:AC 97 Rev 2 Codec with Sample Rate Conversion and National 3D Sound |
| LM4546A | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:AC 97 Rev 2 Multi-Channel Audio Codec with Sample Rate Conversion and National 3D Sound |
| LM4546AVH | 制造商:Rochester Electronics LLC 功能描述:AC97 REV2 CODEC 3D STEREO - Bulk |
| LM4546AVH/NOPB | 制造商:Texas Instruments 功能描述:Audio Codec 2ADC / 2DAC 18-Bit 48-Pin LQFP |
| LM4546AVHX | 制造商:Rochester Electronics LLC 功能描述:AC97 REV2 CODEC 3D STEREO - Bulk |
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