參數(shù)資料
型號: LM4851LQ/NOPB
廠商: NATIONAL SEMICONDUCTOR CORP
元件分類: 音頻/視頻放大
英文描述: 1.5 W, 3 CHANNEL, AUDIO AMPLIFIER, QCC24
封裝: LLP-24
文件頁數(shù): 7/22頁
文件大小: 1126K
代理商: LM4851LQ/NOPB
Application Information (Continued)
SPI OPERATIONAL REQUIREMENTS
1. The data bits are transmitted with the LSB first.
2. The maximum clock rate is 10MHz for the CLK pin.
3. CLK must remain logic-high for at least 50ns (t
CH ) after
the rising edge of CLK, and CLK must remain logic-low for at
least 50ns (t
CL) after the falling edge of CLK.
4. The serial data bits are sampled at the rising edge of CLK.
Any transition on DATA must occur at least 20ns (t
DS) before
the rising edge of CLK. Also, any transition on DATA must
occur at least 20ns (t
DH) after the rising edge of CLK and
stabilize before the next rising edge of CLK.
5. ENB should be logic-high only during serial data transmis-
sion.
6. ENB must be logic-high at least 20ns (t
ES ) before the first
rising edge of CLK, and ENB has to remain logic-high at
least 20ns (t
EH) after the eighth rising edge of CLK.
7. If ENB remains logic-low for more than 10ns before all 8
bits are transmitted then the data latch will be aborted.
8. If ENB is logic-high for more than 8 CLK pulses then only
the first 8 data bits will be latched and activated when ENB
transitions to logic-low.
9. ENB must remain logic-low for at least 30ns (t
EL ) after all
8 bits are transmitted to latch in the data.
10. Coincidental rising or falling edges of CLK and ENB are
not allowed. If CLK is to be held logic-high after the data
transmission, the falling edge of CLK must occur at least
20ns (t
CS) before ENB transitions to logic-high for the next
set of data.
EXPOSED-DAP MOUNTING CONSIDERATIONS
The LM4851’s exposed-DAP (die attach paddle) package
(LQ) provides a low thermal resistance between the die and
the PCB to which the part is mounted and soldered. This
allows rapid heat transfer from the die to the surrounding
PCB copper area heatsink, copper traces, ground plane, and
finally, surrounding air. The result is a low voltage audio
power amplifier that produces 1.1W dissipation in an 8
load
at
≤ 1% THD+N. This high power is achieved through careful
consideration of necessary thermal design. Failing to opti-
mize thermal design may compromise the LM4851’s high
power performance and activate unwanted, though neces-
sary, thermal shutdown protection.
The LQ package must have its DAP soldered to a copper
pad on the PCB. The DAP’s PCB copper pad is then, ideally,
connected to a large plane of continuous unbroken copper.
This plane forms a thermal mass, heat sink, and radiation
area. Place the heat sink area on either outside plane in the
case of a two-sided or multi-layer PCB. (The heat sink area
can also be placed on an inner layer of a multi-layer board.
The thermal resistance, however, will be higher.) Connect
the DAP copper pad to the inner layer or backside copper
heat sink area with 6 (3 X 2) (LQ) vias. The via diameter
should be 0.012in - 0.013in with a 1.27mm pitch. Ensure
efficient thermal conductivity by plugging and tenting the vias
with plating and solder mask, respectively.
Best thermal performance is achieved with the largest prac-
tical copper heat sink area. If the heatsink and amplifier
share the same PCB layer, a nominal 2.5in
2 (min) area is
necessary for 5V operation with a 4
load. Heatsink areas
not placed on the same PCB layer as the LM4851 should be
5in
2 (min) for the same supply voltage and load resistance.
The last two area recommendations apply for 25C ambient
temperature. Increase the area to compensate for ambient
temperatures above 25C. In all circumstances and under all
conditions, the junction temperature must be held below
150C to prevent activating the LM4851’s thermal shutdown
protection. Further detailed and specific information con-
cerning PCB layout and fabrication and mounting an LQ
(LLP) is found in National Semiconductor’s AN1187.
PCB LAYOUT AND SUPPLY REGULATION
CONSIDERATIONS FOR DRIVING 3
AND 4 LOADS
Power dissipated by a load is a function of the voltage swing
across the load and the load’s impedance. As load imped-
ance decreases, load dissipation becomes increasingly de-
pendent on the interconnect (PCB trace and wire) resistance
between the amplifier output pins and the load’s connec-
tions. Residual trace resistance causes a voltage drop,
which results in power dissipated in the trace and not in the
load as desired. For example, 0.1
trace resistance reduces
the output power dissipated by a 4
load from 1.7W to 1.6W.
The problem of decreased load dissipation is exacerbated
20040850
FIGURE 2. SPI Timing Diagram
LM4851
www.national.com
15
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