參數(shù)資料
型號: LM4855ITL/NOPB
廠商: National Semiconductor
文件頁數(shù): 8/27頁
文件大?。?/td> 0K
描述: IC AMP AUDIO PWR 1.5W AB 18USMD
標(biāo)準(zhǔn)包裝: 1
系列: Boomer®
類型: AB 類
輸出類型: 1-通道(單聲道),帶立體聲耳機(jī)
在某負(fù)載時最大輸出功率 x 通道數(shù)量: 1.5W x 1 @ 4 歐姆; 115mW x 2 @ 32 歐姆
電源電壓: 2.6 V ~ 5 V
特點(diǎn): 消除爆音,靜音,關(guān)機(jī),SPI,熱保護(hù),音量控制
安裝類型: 表面貼裝
供應(yīng)商設(shè)備封裝: 18-uSMD
封裝/外殼: 18-WFBGA
包裝: 標(biāo)準(zhǔn)包裝
其它名稱: LM4855ITLDKR
SNAS164C – JUNE 2002 – REVISED MAY 2013
SPI OPERATIONAL REQUIREMENTS
1. The data bits are transmitted with the LSB first.
2. The maximum clock rate is 10MHz for the CLK pin.
3. CLK must remain logic-high for at least 50ns (tCH ) after the rising edge of CLK, and CLK must remain logic-
low for at least 50ns (tCL) after the falling edge of CLK.
4. The serial data bits are sampled at the rising edge of CLK. Any transition on DATA must occur at least 20ns
(tDS) before the rising edge of CLK. Also, any transition on DATA must occur at least 20ns (tDH) after the rising
edge of CLK and stabilize before the next rising edge of CLK.
5. ENB should be logic-high only during serial data transmission.
6. ENB must be logic-high at least 20ns (tES ) before the first rising edge of CLK, and ENB has to remain logic-
high at least 20ns (tEH) after the eighth rising edge of CLK.
7. If ENB remains logic-low for more than 10ns before all 8 bits are transmitted then the data latch will be
aborted.
8. If ENB is logic-high for more than 8 CLK pulses then only the first 8 data bits will be latched and activated
when ENB transitions to logic-low.
9. ENB must remain logic-low for at least 30ns (tEL ) to latch in the data.
10. Coincidental rising or falling edges of CLK and ENB are not allowed. If CLK is to be held logic-high after the
data transmission, the falling edge of CLK must occur at least 20ns (tCS) before ENB transitions to logic-high for
the next set of data.
Figure 37. SPI Timing Diagram
16
Copyright 2002–2013, Texas Instruments Incorporated
Product Folder Links: LM4855
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