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參數(shù)資料
| 型號(hào)： | LM4855LQ/NOPB |
| 廠商： | National Semiconductor |
| 文件頁(yè)數(shù)： | 6/27頁(yè) |
| 文件大小： | 0K |
| 描述： | IC AMP AUDIO PWR 1.5W MONO 24LLP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | Boomer® |
| 類(lèi)型： | AB 類(lèi) |
| 輸出類(lèi)型： | 1-通道（單聲道），帶立體聲耳機(jī) |
| 在某負(fù)載時(shí)最大輸出功率 x 通道數(shù)量： | 1.5W x 1 @ 4 歐姆; 115mW x 2 @ 32 歐姆 |
| 電源電壓： | 2.6 V ~ 5 V |
| 特點(diǎn)： | 消除爆音，靜音，關(guān)機(jī)，SPI，熱保護(hù)，音量控制 |
| 安裝類(lèi)型： | 表面貼裝 |
| 供應(yīng)商設(shè)備封裝： | 24-LLP-EP（4x5） |
| 封裝/外殼： | 24-WFQFN 裸露焊盤(pán) |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 配用： | LM4855LQBD-ND - BOARD EVALUATION LM4855LQ |
| 其它名稱(chēng)： | LM4855LQDKR |
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SNAS164C – JUNE 2002 – REVISED MAY 2013
APPLICATION INFORMATION
SPI PIN DESCRIPTION
DATA: This is the serial data input pin.
CLK: This is the clock input pin.
ENB: This is the SPI enable pin and is active-high.
SPI OPERATION DESCRIPTION
The serial data bits are organized into a field which contains 8 bits of data defined by Table 2. The Data 0 to
Data 2 bits determine the output mode of the LM4855 as shown in Table 3. The Data 3 to Data 7 bits determine
the volume level setting as illustrated by Table 4. For each SPI transfer, the data bits are written to the DATA pin
with the least significant bit (LSB) first. All serial data are sampled at the rising edge of the CLK signal. Once all
the data bits have been sampled, ENB transitions from logic-high to logic-low to complete the SPI sequence. All
8 bits must be received before any data latch can occur. Any excess CLK and DATA transitions will be ignored
after the eighth rising clock edge has occurred. For any data sequence longer than 8 bits, only the first 8 bits will
get loaded into the shift register and the rest of the bits will be disregarded.
Table 2. Bit Allocation
Data 0
Mode Select
Data 1
Mode Select
Data 2
Mode Select
Data 3
Volume Control
Data 4
Volume Control
Data 5
Volume Control
Data 6
Volume Control
Data 7
Volume Control
Table 3. Output Mode Selection(1)
Output Mode #
Data 2
Data 1
Data 0
SPKROUT
ROUT
LOUT
0
SD
1
0
1
12dB x PIHF
SD
2
0
1
0
MUTE
G1 x PHS
3
0
1
12dB x PIHF
G1 x PHS
4
1
0
MUTE
G2 x R
G2 x L
5
1
0
1
12dB x PIHF
G2 x R
G2 x L
6
1
0
MUTE
(G1 x PHS) + (G2
x R)
x L)
7
1
12dB x PIHF
(G1 x PHS) + (G2
x R)
x L)
(1)
R = Rin
L = Lin
PIHF = Phone_In_IHF
PHS = Phone_In_HS
SD = Shutdown Mode
MUTE = Mute Mode
G1 = gain from PHS to LOUT/ROUT
G2 = gain from LIN/ RIN to LOUT/ROUT
Default Mode upon device power-up is Output Mode 0
14
Copyright 2002–2013, Texas Instruments Incorporated
Product Folder Links: LM4855
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