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參數(shù)資料
| 型號： | LM4856LQ/NOPB |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 音頻／視頻放大 |
| 英文描述： | 1.5 W, 3 CHANNEL, AUDIO AMPLIFIER, QCC24 |
| 封裝： | LLP-24 |
| 文件頁數(shù)： | 6/23頁 |
| 文件大小： | 1321K |
| 代理商： | LM4856LQ/NOPB |
Application Information
I
2C PIN DESCRIPTION
SDA: This is the serial data input pin.
SCL: This is the clock input pin.
ADR: This is the address select input pin.
I
2C INTERFACE
The LM4856 uses a serial bus, which conforms to the I
2C
protocol, to control the chip’s functions with two wires: clock
and data. The clock line is uni-directional. The data line is
bi-directional (open-collector) with a pullup resistor (typically
10k
).The maximum clock frequency specified by the I2C
standard is 400kHz. In this discussion, the master is the
controlling microcontroller and the slave is the LM4856.
The I
2C address for the LM4856 is determined using the
ADR pin. The LM4856’s two possible I
2C chip addresses are
of the form 110110X
10 (binary), where the X1 = 0, if ADR is
logic low; and X
1 = 1, if ADR is logic high. If the I
2C interface
is used to address a number of chips in a system and the
LM4856’s chip address can be changed to avoid address
conflicts.
The timing diagram for the I
2C is shown in Figure 2. The data
is latched in on the stable high level of the clock and the data
line should be held high when not in use. The timing diagram
is broken up into six major sections:
The “start” signal is generated by lowering the data signal
while the clock signal is high. The start signal will alert all
devices attached to the I
2C bus to check the incoming ad-
dress against their own chip address.
The 8-bit chip address is sent next, most significant bit first.
Each address bit must be stable while the clock level is high.
After the last bit of the address is sent, the master checks for
the LM4856’s acknowledge. The master releases the data
line high (through a pullup resistor). Then the master sends
a clock pulse. If the LM4856 has received the address
correctly, then it holds the data line low during the clock
pulse. If the data line is not low, then the master should send
a “stop” signal (discussed later) and abort the transfer.
The 8 bits of data are sent next, most significant bit first.
Each data bit should be valid while the clock level is stable
high.
After the data byte is sent, the master must generate another
acknowledge to see if the LM4856 received the data.
If the master has more data bytes to send to the LM4856,
then the master can repeat the previous two steps until all
data bytes have been sent.
The “stop” signal ends the transfer. To signal “stop”, the data
signal goes high while the clock signal is high.
200607F5
FIGURE 2. I
2C Bus Format
200607F4
FIGURE 3. I
2C Timing Diagram
LM4856
www.national.com
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LM4857 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Stereo 1.2W Audio Sub-system with 3D Enhancement |
| LM4857_05 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Stereo 1.2W Audio Sub-system with 3D Enhancement |
| LM4857GR | 功能描述:IC AUDIO SUBSYSTEM W/3D 49UBGA RoHS:否 類別:集成電路 (IC) >> 線性 - 音頻放大器 系列:Boomer® 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:2,500 系列:DirectDrive® 類型:H 類 輸出類型:耳機，2-通道（立體聲） 在某負(fù)載時最大輸出功率 x 通道數(shù)量:35mW x 2 @ 16 歐姆 電源電壓:1.62 V ~ 1.98 V 特點:I²C，麥克風(fēng)，靜音，短路保護(hù)，音量控制 安裝類型:表面貼裝 供應(yīng)商設(shè)備封裝:25-WLP（2.09x2.09） 封裝/外殼:25-WFBGA，WLCSP 包裝:帶卷 (TR) |
| LM4857ITL | 制造商:Texas Instruments 功能描述:1.2W STEREO SUBSYST 3D SMD 4857 |
| LM4857ITL/NOPB | 功能描述:音頻放大器 RoHS:否 制造商:STMicroelectronics 產(chǎn)品:General Purpose Audio Amplifiers 輸出類型:Digital 輸出功率: THD + 噪聲: 工作電源電壓:3.3 V 電源電流: 最大功率耗散: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TQFP-64 封裝:Reel |
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