參數(shù)資料
型號(hào): LM5030MM
廠商: NATIONAL SEMICONDUCTOR CORP
元件分類: 穩(wěn)壓器
英文描述: 100V Push-Pull Current Mode PWM Controller
中文描述: SWITCHING CONTROLLER, 690 kHz SWITCHING FREQ-MAX, PDSO10
封裝: MSOP-10
文件頁數(shù): 8/11頁
文件大?。?/td> 230K
代理商: LM5030MM
Current Limit/ Current Sense
(Continued)
In this case all of the noise sensitive low power grounds
should be commoned together around the IC and then a
single connection should be made to the power ground
(sense resistor ground point).
The second level threshold is intended to protect the power
converter by initiating a low duty cycle hiccup mode when
abnormally high, fast rising currents occur. During excessive
loading, the first level threshold will always be reached and
the output characteristic of the converter will be that of a
current source but this sustained current level can cause
excessive temperatures in the power train especially the
output rectifiers. If the second level threshold is reached, the
softstart capacitor will be fully discharged, a retry will com-
mence following the discharge detection. The second level
threshold will only be reached when a high dV/dt is present
at the current sense pin. The signal must be fast enough to
reach the second level threshold before the first threshold
detector turns off the driver. This can usually happen for a
saturated power inductor or shorted load. Excessive filtering
on the CS pin, extremely low value current sense resistor or
an inductor that does not saturate with excessive loading
may prevent the second level threshold from ever being
reached.
Oscillator, Shutdown and Sync
Capability
The LM5030 oscillator is set by a single external resistor
connected between the RT pin and return. To set a desired
oscillator frequency the necessary RT resistor can be calcu-
lated as:
Each output switches at half the oscillator frequency in a
Push-Pull configuration. The LM5030 can also be synchro-
nized to an external clock. The external clock must be of
higher frequency than the free running frequency set by the
RT resistor. The clock signal should be capacitively coupled
into the RT pin with a 100pF capacitor. A peak voltage level
greater than 3 Volts with respect to ground is required for
detection of the sync pulse. The sync pulse width should be
set in the 15 to 150nS range by the external components.
The RT resistor is always required, whether the oscillator is
free running or externally synchronized. The voltage at the
RT pin is internally regulated to a nominal 2 Volts.
The RT resistor should be located very close to the device
and connected directly to the pins of the IC (RT and GND).
Slope Compensation
The PWM comparator compares the current sense signal to
the voltage derived from the COMP pin. The COMP voltage
is set by either the internal error amplifier or an external error
amplifier through an optocoupler. At duty cycles greater than
50% (composite of alternating outputs) current mode control
circuits are prone to subharmonic oscillation. By adding an
additional ramp signal to the current sense ramp signal this
condition can be avoided. The LM5030 integrates this slope
compensation by buffering the internal oscillator ramp and
summing it internally to the current sense (CS) signal. Addi-
tional slope compensation may be added by increasing the
source impedance of the current sense signal.
Soft Start/ Shutdown
The softstart feature allows the converter to gradually reach
the initial steady state operating point, thus reducing start-up
stresses and surges. An internal 10uA current source and an
external capacitor generate a ramping voltage signal which
limits the error amplifier output during start-up. In the event
of a second level current limit fault, the softstart capacitor will
be fully discharged which disables the output drivers. When
the fault condition is no longer present, the softstart capaci-
tor is released to ramp and gradually restart the converter.
The SS pin can also be used to disable the controller. If the
SS pin voltage is pulled down below 0.45V (nominal) the
controller will disable the outputs and enter a low power
state.
OUT1, OUT2 and Time Delay
The LM5030 provides two alternating outputs, OUT1 and
OUT2. The internal gate drivers can each sink 1.5A peak
each. The maximum duty cycle for each output is inherently
limited to less than 50%. The typical deadtime between the
falling edge of one gate driver output and the rising edge of
the other gate driver output is 135ns.
Thermal Protection
Internal Thermal Shutdown circuitry is provided to protect the
integrated circuit in the event the excessive junction tem-
perature. When activated, typically at 165 degrees Celsius,
the controller is forced into a low power reset state, disabling
the output drivers and the bias regulator. This feature is
provided to prevent catastrophic failures from accidental
device overheating.
L
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