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參數(shù)資料
| 型號： | LM78CCVF-J |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 模擬信號調(diào)理 |
| 英文描述： | Microprocessor System Hardware Monitor |
| 中文描述： | SPECIALTY ANALOG CIRCUIT, PQFP44 |
| 封裝： | 10 X 10 MM, PLASTIC, QFP-44 |
| 文件頁數(shù)： | 12/31頁 |
| 文件大?。?/td> | 424K |
| 代理商： | LM78CCVF-J |
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Functional Description
(Continued)
2.0 INTERFACE
The LM78 only decodes the three lowest address bits on the
ISA bus. Referring to the ISA bus timing diagrams in Figure
1 and Figure 2 the Chip Select Input, CS, should be taken
low by external address decoder circuitry to access the
LM78. The LM78 decodes the following base addresses:
-Port x0h: Power On Self Test codes from ISA bus.
-Port x4h: Power On Self Test codes from ISA bus.
-Port x5h: The LM78s Internal Address Register
-Port x6h: Data Register
IORD is the standard ISA bus signal that indicates to the
LM78 that it may drive data on to the ISA data bus.
IOWR is the standard ISA command to the LM78 that it may
latch data from the ISA bus.
SYSCLK is the standard ISA SYSCLK, typically 8.33 MHz.
This clock is used only for timing of the ISA interface of the
LM78.All other clock functions within LM78 such as theADC
and fan counters are done with a separate asynchronous
internal clock.
A typical application designed to utilize the POST RAM
would decode the LM78 to the address space starting at
80h, which is where POST codes are output to. Otherwise,
the LM78 can be decoded into a different desired address
space.
To communicate with an LM78 Register, first write the ad-
dress of that Register to Port x5h. Read or write data from or
to that register via Port x6h. A write will take IOWR low, while
a read will take IORD low.
If the Serial Bus Interface and ISA bus interface are used
simultaneously there is the possibility of collision. To prevent
this from occurring in applications where both interfaces are
used, read port x5h and if the Most Significant Bit, D7, is
high, ISA communication is limited to reading port x5h only
until this bit is low. A Serial Bus communication occurring
while ISA is active will not be a problem, since even a single
bit of Serial Bus communication requires 10 microseconds,
in comparison to less than a microsecond for an entire ISA
communication.
L
www.national.com
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