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參數資料
| 型號： | LM81CIMT-31 |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | Serial Interface ACPI-Compatible Microprocessor System |
| 中文描述： | 串行接口ACPI的兼容微處理器系統 |
| 文件頁數： | 21/32頁 |
| 文件大?。?/td> | 412K |
| 代理商： | LM81CIMT-31 |
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Functional Description
(Continued)
9.0 THE LM81 INTERRUPT STRUCTURE
Figure 17 depicts the Interrupt Structure of the LM81. The
LM81 can generate Interrupts as a result of each of its inter-
nal WATCHDOG registers on the analog, temperature, and
fan inputs.
External Interrupts can come from the following source.
While the label suggests a specific type or source of Inter-
rupt, this label is not a restriction of its usage, and it could
come from any desired source:
Chassis Intrusion:
This is an active high interrupt
from any type of device that detects and captures chassis
intrusion violations. This could be accomplished me-
chanically, optically, or electrically, and circuitry external
to the LM81 is expected to latch the event. The design of
the LM81 allows this input to go high even with no power
applied to the LM81, and no clamping or other interfer-
ence with the line will occur. This line can also be pulled
low for at least 20 ms by the LM81 to reset a typical
Chassis Intrusion circuit. Accomplish this reset by setting
Bit 7 of CI Clear Register (45h) high. The bit in the Reg-
ister is self-clearing.
All interrupts are indicated in the two Interrupt Status Regis-
ters. The INT output has two mask registers, and individual
masks for each Interrupt. As described in Section 3.3, the
hardware Interrupt line can also be enabled/disabled in the
Configuration Register.
DS100072-22
FIGURE 17. Interrupt Structure
www.national.com
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