![](http://datasheet.mmic.net.cn/230000/LM9011_datasheet_15593369/LM9011_13.png)
Circuit Description
(Continued)
The Electronic Timing Interface provide signals to the spark
module from the micro-processor. The interface requires four
input data signals, and provides four output control chan-
nels.
The interface also provides one output channel for diagnos-
tic information for any open or shorted loads on S1 to S4.
The RESET pin has an internal pull-up resistor to V
of typi-
cally 100K
, and the ENB pin has an internal pull-down re-
sistor to ground of typically 100K
.
To put the outputs into the TRI-STATE mode at power-on,
the RESET pin should be held low until V
is above 4.75V.
This can be accomplished by micro-processor control, or by
adding a capacitor from the RESET pin to ground.
The RESET pin is used to disable the spark driver outputs by
putting them in a TRI-STATE mode. While in the TRI-STATE
mode the Open Output Fault detection circuitry is active. An
open Output is detected by forcing a small current (I
)
through the outputs to the loads, and monitoring the voltage
on the output pins rises above the Output Fault Threshold
Voltage (V
FAULT
) the FAULT pin will be forced low. The intent
is to detect an open wire condition, and not necessarily to
detect a local resistance threshold.
Note that if any output has a Short to battery fault, the fault
pin will go low during this TRI-STATE mode. The internal
comparator is unable to discern why an output pin may be
above the Fault Threshold Voltage, only that it is. In any
case, a fault is reported, even if it is not the anticipated fault.
The TRI-STATE mode is a latched condition. For the outputs
to come out of the TRI-STATE mode, the RESET pin must be
high, and then the data input pin D0 must toggle from a low
state to a high state. The state of the outputs will now be set
by the data inputs D0 and D1, and the ENB input. If ENB is
low when the TRI-STATE mode is cleared, all of the outputs
will go low.
Pins D0 and D1 are used select an output, and ENB will en-
able the selected output. The outputs have have active pull
up to S_HI, and the active pull down to Ground. The default
not enabled output conditions is low, and the enabled output
condition is high. Only one output can be enabled (high) at a
time. The outputs are not latched in any state and will follow
the input selected with D0 and D1 as long as ENB is high.
The detection of an output shorted to ground, or battery, is
dependent on the status of ENB. While ENB is logical 0, all
of the outputs are forced low and the Short to Battery fault
detection circuitry is active. A Short to Battery is detected by
monitoring the voltage on the output pins. If the voltage on
any output pin is above the Fault Threshold Voltage (V
)
the FAULT pin will go low. The output current sink is limited
to typically 8mA. The short to battery condition must be able
to provide enough current to overcome the current limit and
raise the output pin voltage above the V
FAULT
threshold.
When ENB is logical 1, the selected output will be high and
the Short to Ground detection circuitry is active. A Short to
Ground is detected by monitoring the voltage on the output
pins. If the voltage on the selected output pin is below the
Fault Threshold Voltage (V
FAULT
) the FAULT pin will go low.
The output current source is from S_HI limited to typically
25mA to 50mA across the S_HI voltage range. The short to
ground condition must be allow enough resistance to allow
the output pin voltage to fall below the V
threshold with
the output sourcing short circuit current. Typically, a short to
ground which has 100 Ohms of resistance, or more, can not
be reliably detected. Typically, a short to ground of 20 Ohms,
or less, can be reliably detected across the entire S_HI volt-
age range and device operating temperature range. Note
that if any output has a Short to Battery fault, a Short to
Electronic Timing Interface
Inputs
Output
RESET
0
1
1
1
1
1
ENB
X
0
1
1
1
1
D0
X
X
0
1
0
1
D1
X
X
0
0
1
1
S1
Tri
L
H
L
L
L
S2
Tri
L
L
H
L
L
S3
Tri
L
L
L
H
L
S4
Tri
L
L
L
L
H
FIGURE 14. Truth Table for Electronic Timing Interface
L
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