參數(shù)資料
型號: LM9040
廠商: National Semiconductor Corporation
英文描述: Dual Lambda Sensor Interface Amplifier
中文描述: 雙氧傳感器接口放大器
文件頁數(shù): 6/10頁
文件大?。?/td> 178K
代理商: LM9040
Common Mode Filtering
(Continued)
For a common mode sine wave signal having a frequency
100 Hz, and with a F
CLOCK
of 100 kHz, the minimum com-
mon mode rejection would be:
CMRR
e
2
#
3.14159
#
100
#
5E-6
#
4.53
CMRR
e
0.014
e b
37 dB
If the common mode sine wave has a peak to peak value of
2V, the maximum voltage error at the output would be:
V
OUT(CM)
e
2V
#
0.014
e
28 mV
As this formula shows, the value of V
OUT(CM)
is proportional
to the frequency of the CMR signal. If the frequency is dou-
bled, the value of V
OUT(CM)
is also doubled. The addition of
a small bypass capacitor (C
CM
) from the non-inverting input
to ground will help counter this problem. SeeFigure 6. How-
ever, the use of this bypass capacitor creates a new prob-
lem in that the differential input is no longer balanced. While
the Lambda sensor is cold (i.e. R
SENSOR
l
10 Meg
X
) there
is little difference in CMR performance. As the Lambda sen-
sor heats to the operating temperature and the sensor re-
sistance decreases, the common mode signal is no longer
applied to both inputs equally. This imbalance causes
V
OUT(CM)
to increase as R
SENSOR
decreases, as the non-
inverting input will see the full common mode signal, while
the non-inverting input will see an attenuated common
mode signal.
The selection of the value of the CMR bypass capacitor
needs to be balanced with the need for reasonable reduc-
tion, or elimination, of common mode signals with both cold
and hot sensors. Since normal operation will need to in-
clude consideration of the entire impedance range of the
sensor, a trade off in overall application performance may
be needed.
Generally, the value of the CMR bypass capacitor should be
kept as low as possible, and should not be larger than the
differential input filter capacitor. Values in the range of
0.001
m
F to 0.01
m
F will usually provide reasonable CMR
results, but optimum results will need to be determined em-
pirically, as the source of common mode signals will be
unique to each application.
Gain and Filter Stage
The signal gain and filter stage is designed to have a DC
gain of 4.53 V/V, with a cut-off frequency of typically
500 Hz. The external 4 k
X
resistors on each input pin are in
series with the differential input impedance. Together they
form a voltage divider circuit across the input such that the
net DC gain of the application circuit is 4.50 V/V.
TL/H/12372–17
FIGURE 7. Simplified Gain and Filter Circuit
The internal gain is set by the ratio of C
IN
and C
FB
:
GAIN
DC
e
C
IN
C
FB
GAIN
DC
e
7.4213 pF
1.6383 pF
e
4.53 V/V
The corner frequency (
b
3 dB) is set by the ratio of C
FB
and
C
INT
, and by F
CLOCK
:
F
C
e
F
CLOCK
#
C
FB
2
#
q
#
C
INT
1E5
#
1.6383E-12
2
#
3.14159
#
52.1E-12
F
C
e
e
500 Hz
TL/H/12372–18
FIGURE 8. Equivalent Gain and Filter Circuit
6
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