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參數(shù)資料
| 型號(hào)： | LM91 |
| 文件頁(yè)數(shù)： | 5/14頁(yè) |
| 文件大?。?/td> | 184K |
| 代理商： | LM91 |
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Logic Electrical Characteristics
DIGITAL DC CHARACTERISTICS
Unless otherwise noted, these specifications apply for V
=+3.0 to 3.6 Vdc.
Boldface limits apply for T
A
= T
J
= T
MIN
to
T
MAX
;
all other limits T
A
= T
J
=+25C, unless otherwise noted.
Symbol
Parameter
Conditions
Typical
(Note 6)
LM91D
Limits
(Note 7)
Units
(Limit)
SMBData, SMBCLK
V
IN(1)
V
IN(0)
I
IN(1)
I
IN(0)
ADD0, ADD1
V
IN(1)
V
IN(0)
I
IN(1)
I
IN(0)
ALL DIGITAL INPUTS
C
IN
ALL DIGITAL OUTPUTS
I
OH
V
OL
Logical “1” Input Voltage
Logical “0”Input Voltage
Logical “1” Input Current
Logical “0” Input Current
2.1
0.8
1.0
1.0
V (min)
V (max)
μA (max)
μA (max)
V
IN
= V
CC
V
IN
= 0V
0.005
0.005
Logical “1” Input Voltage
Logical “0”Input Voltage
Logical “1” Input Current
Logical “0” Input Current
V
CC
GND
50
50
1.6
0.5
600
600
V (min)
V (max)
μA (max)
μA (max)
V
IN
= V
CC
V
IN
= 0V
Input Capacitance
20
pF
High Level Output Current
SMBus Low Level Output Voltage
V
OH
= V
CC
I
OL
= 3 mA
I
OL
= 6 mA
100
0.4
0.6
μA (max)
V (max)
SMBus DIGITAL SWITCHING CHARACTERISTICS
Unless otherwise noted, these specifications apply for V
CC
=+3.0 Vdc to +3.6 Vdc, C
(load capacitance) on output lines = 80
pF.
Boldface limits apply for T
= T
= T
to T
;
= T
= +25C, unless otherwise noted.
The switching characteristics of the LM91 fully meet or exceed the published specifications of the SMBus or I
2
C bus. The fol-
lowing parameters are the timing relationships between SMBCLK and SMBData signals related to the LM91. They are not nec-
essarily the I
2
C or SMBus bus specifications.
Symbol
Parameter
Conditions
Typical
(Note 6)
Limits
(Note 7)
400
10
1.3
25
25
0.6
Units
(Limit)
kHz (max)
kHz (min)
μs (min)
ms (max)
ms (max)
μs (min)
μs
μs
ns (max)
f
SMB
SMBus Clock Frequency
t
LOW
SMBus Clock Low Time
10% to 10%
t
LOW
SEXT Cumulative Clock Low Extend Time
t
HIGH
SMBus Clock High Time
t
R;SMB
SMBus Rise Time
t
F;SMB
SMBus Fall Time
t
OF
Output Fall Time
90% to 90%
10% to 90%
90% to 10%
C
L
= 400 pF
I
O
= 3 mA
1
0.3
250
t
TIMEOUT
SMBData and SMBCLK Time Low for
Reset of Serial Interface (Note 12)
SMBCLK (Clock) Period
Data In Setup Time to SMBCLK High
25
40
2.5
100
ms (min)
ms (max)
μs (min)
ns (min)
t
1
t
2
,
t
SU;DAT
t
3
,
t
HD;DAT
t
4
,
t
HD;STA
t
5
,
t
SU;STO
t
6
,
t
SU;STA
Data Out Stable after SMBCLK Low
0
0.9
100
ns (min)
μs (max)
ns (min)
SMBData Low Setup Time to SMBCLK
Low
SMBData High Delay Time after SMBCLK
High (Stop Condition Setup)
SMBus Start-Condition Setup Time
100
ns (min)
0.6
μs (min)
L
www.national.com
5
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