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9.0 Pin Descriptions
Symbol
PROCHOT
Pin #
1
Type
Digital I/O (Open-
Drain)
Function
Connected to CPU1 PROCHOT (processor hot) signal through a
bidirectional level shifter. Supports TTL input logic levels and AGTL
compatible input logic levels.
All grounds need to be tied together at the chip then taken to a low noise
system ground. A voltage difference between grounds may cause
erroneous results.
All grounds need to be tied together at the chip then taken to a low noise
system ground. A voltage difference between grounds may cause
erroneous results.
All grounds need to be tied together at the chip then taken to a low noise
system ground. A voltage difference between grounds may cause
erroneous results.
All grounds need to be tied together at the chip then taken to a low noise
system ground. A voltage difference between grounds may cause
erroneous results.
All grounds need to be tied together at the chip then taken to a low noise
system ground. A voltage difference between grounds may cause
erroneous results.
Can be configured as fan tach input or a general purpose open-drain digital
I/O.
Can be configured as fan tach input or a general purpose open-drain digital
I/O.
Can be configured as fan tach input or a general purpose open-drain digital
I/O.
Can be configured as fan tach input or a general purpose open-drain digital
I/O..
A general purpose open-drain digital I/O. Can be configured to monitor a
CPU's THERMTRIP signal to mask other errors. Supports TTL input logic
levels and AGTL compatible input logic levels.
A general purpose open-drain digital I/O. Supports TTL input logic levels
and AGTL compatible input logic levels.
Can be used to detect the state of CPU's IERR or a general purpose open-
drain digital I/O. Supports TTL input logic levels and AGTL compatible input
logic levels.
A general purpose open-drain digital I/O. Supports TTL input logic levels
and AGTL compatible input logic levels.
CPU1 voltage regulator HOT. Supports TTL input logic levels and AGTL
compatible input logic levels.
All grounds need to be tied together at the chip then taken to a low noise
system ground. A voltage difference between grounds may cause
erroneous results.
CPU VID6 input. Could also be used as a general purpose input to trigger
an error event. Supports TTL input logic levels and AGTL compatible input
logic levels.
Bidirectional System Management Bus Data. Output configured as 5V
tolerant open-drain. SMBus 2.0 compliant.
System Management Bus Clock. Driven by an open-drain output, and is 5V
tolerant. SMBus 2.0 Compliant.
Open-drain ALERT output used in an interrupt driven system to signal that
an error event has occurred. Masked error events do not activate the
ALERT output. When in XOR tree test mode, functions as XOR Tree output.
GND
2
Ground
GND
3
Ground
GND
4
Ground
GND
5
Ground
GND
6
Ground
GPIO_0/TACH1
7
Digital I/O (Open-
Drain)
Digital I/O (Open-
Drain)
Digital I/O (Open-
Drain)
Digital I/O (Open-
Drain)
Digital I/O (Open-
Drain)
GPIO_1/TACH2
8
GPIO_2/TACH3
9
GPIO_3/TACH4
10
GPIO_4 / THERMTRIP 11
GPIO_5
12
Digital I/O (Open-
Drain)
Digital I/O (Open-
Drain)
GPIO_6
13
GPIO_7
14
Digital I/O (Open-
Drain)
Digital Input
VRD1_HOT
15
GND
16
Ground Input
VID6/GPI9
17
Digital Input
SMBDAT
18
Digital I/O (Open-
Drain)
Digital Input
SMBCLK
19
ALERT/XtestOut
20
Digital Output (Open-
Drain)
5
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