參數資料
型號： LM9801
廠商： National Semiconductor Corporation
英文描述： Greyscale/24-Bit Color Linear CCD Sensor Processor
中文描述： Greyscale/24-Bit彩色線陣CCD傳感器處理器
文件頁數： 8/34頁
文件大?。?/td> 520K
代理商： LM9801
Pin Descriptions
CCD Driver Signals
w
1
Digital Output. CCD clock signal, phase 1.
w
2
Digital Output. CCD clock signal, phase 2.
RS
Digital Output. Reset pulse for the CCD.
TR
Digital Output. Transfer pulse for the CCD.
Analog I/O
OS
Analog Input. This is the OS (Output
Signal) from the CCD. The maximum peak
signal that can be accurately digitized is
equal to the voltage at REF IN, typically
1.225V.
REF IN
Analog Inputs. These two pins are the
system reference voltage inputs and
should be tied together to a 1.225V voltage
source and bypassed to AGND with a 0.1
m
F monolithic capacitor.
REF OUT
HI
Analog Output. This reference voltage is
developed internally by the LM9801, and is
equal to 3 times REF IN. It should be
bypassed to AGND with a 0.1
m
F
monolithic capacitor.
REF OUT
MID
Analog Output. This reference voltage is
developed internally by the LM9801, and is
equal to 2 times REF IN. It should be
bypassed to AGND using a 0.1
m
F
monolithic capacitor.
V
TEST1
,
V
TEST2
Analog Inputs/Outputs. These pins are
used for testing the device during
manufacture and should be left
unconnected.
General Digital I/O
MCLK
Digital Input. This is the 20 MHz (typical)
master system clock.
SYNC
Digital Input. A low-to-high transition on this
input begins a line scan operation. The line
scan operation terminates when this input
is taken low.
Configuration Register I/O
SDI
Digital Input. Serial Data Input pin.
SDO
Digital Output. Serial Data Output pin.
SCLK
Digital Input. This is the serial data clock,
used to clock data in through SDI and out
through SDO. SCLK is asynchronous to
MCLK. Input data is latched and output
data is changed on the rising edge of
SCLK.
CS
Digital Input. This is the Chip Select signal
for writing to the Configuration Register
through the serial interface. This input must
be low in order to communicate with the
Configuration Register. This pin is used for
serial I/O only–it has no effect on any
other section of the chip.
Digital Coefficient I/O
CD0 (LSB)–
CD7 (MSB)
Digital Inputs. Correction Coefficient
Databus. This is the 8-bit data path for the
gain adjust PGA, used during line scan.
CCLK
Digital Output. This is the signal that is used
to clock the Gain coefficients into the
LM9801. Data is latched on the rising edge
of CCLK.
Digital Output I/O
DD0 (LSB)–
DD7 (MSB)
Digital Outputs. Pixel Output Databus. This
data bus outputs the 8-bit digital output data
during line scan.
EOC
Digital Output. This is the End of Conversion
signal from the ADC indicating that new
pixel data is available.
RD
Digital Input. Taking this input low places
the data stored in the output latch on the
bus. When this input is high the DD0–DD7
bus is in TRI-STATE.
Analog Power
V
A
This is the positive supply pin for the analog
supply. It should be connected to a voltage
source of
a
5V and bypassed to AGND with
a 0.1
m
F monolithic capacitor in parallel with
a 10
m
F tantalum capacitor.
AGND
This is the ground return for the analog
supply.
Digital Power
V
D
This is the positive supply pin for the digital
supply. It should be connected to a voltage
source of
a
5V and bypassed to DGND with
a 0.1
m
F monolithic capacitor.
DGND
This is the ground return for the digital
supply.
V
D(I/O)
This is the positive supply pin for the digital
supply for the LM9801’s I/O. It should be
connected to a voltage source of
a
3V to
a
5V and bypassed to DGND
(I/O)
with a
0.1
m
F monolithic capacitor. If the supply for
this pin is different than the supply for V
A
and V
D
, it should also be bypassed with a
10
m
F tantalum capacitor.
DGND
(I/O)
This is the ground return for the digital
supply for the LM9801’s I/O.
NC
NC
All pins marked NC (no connect) should be
left floating. Do not tie NC pins to ground.,
power supplies, or any other potential or
signal.
http://www.national.com
8
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