參數(shù)資料
型號: LM9801CCV
廠商: NATIONAL SEMICONDUCTOR CORP
元件分類: 模擬信號調(diào)理
英文描述: Greyscale/24-Bit Color Linear CCD Sensor Processor
中文描述: SPECIALTY ANALOG CIRCUIT, PQCC52
封裝: PLASTIC, LCC-52
文件頁數(shù): 6/34頁
文件大小: 520K
代理商: LM9801CCV
AC Electrical Characteristics, MCLK Independent
(Continued)
The following specifications apply for AGND
e
DGND
e
DGND
(I/O)
e
0V, V
A
e
V
D
e
V
D(I/O)
e a
5.0V
DC
, REF IN
e
a
1.225V
DC
, f
MCLK
e
20 MHz, t
MCLK
e
1/f
MCLK
, t
r
e
t
f
e
5 ns, R
s
e
25
X
, C
L
(databus loading)
e
50 pF/pin.
Boldface
limits apply for T
A
e
T
J
e
T
MIN
to T
MAX
; all other limits T
A
e
T
J
e
25
§
C. (Notes 7 and 8)
Symbol
Parameter
Conditions
Typical
(Note 9)
Limits
(Note 10)
Units
(Limits)
t
S1H
, t
S0H
Delay from CS Rising Edge to SDO
TRI-STATE
R
L
e
3k, C
L
e
50 pF
25
50
ns (max)
t
RDO
SDO Rise Time, TRI-STATE to High
SDO Rise Time, Low to High
R
L
e
3k, C
L
e
50 pF
20
20
ns
ns
t
FDO
SDO Fall Time, TRI-STATE to Low
SDO Fall Time, High to Low
R
L
e
3k, C
L
e
50 pF
20
20
ns
ns
AC Electrical Characteristics, MCLK Dependent
The following specifications apply for AGND
e
DGND
e
DGND
(I/O)
e
0V, V
A
e
V
D
e
V
D(I/O)
e a
5.0V
DC
, REF IN
e
a
1.225V
DC
, f
MCLK
e
20 MHz, t
MCLK
e
1/f
MCLK
, t
r
e
t
f
e
5 ns, R
s
25
X
, C
L
(databus loading)
50 pF/pin. Refer to
Table
2, Configuration Register Parameters,
for limits labelled
C.R. Boldface limits apply for T
A
e
T
J
e
T
MIN
to
T
MAX
; all other limits T
A
e
T
J
e
25
§
C. (Notes 7 and 8)
Symbol
Parameter
Conditions
Typical
(Note 9)
Limits
(Note 10)
Units
(Limits)
t
START
MCLK to first
w
1 High
50 ns
1
t
MCLK
t
w
w
1,
w
2 Clock Period
Standard CCD Mode
Even/Odd CCD Mode
400 ns
800 ns
8
16
t
MCLK
t
MCLK
t
TRWIDTH
Transfer Pulse (TR) Width
C.R.
m
s
t
GUARD
w
1 to TR, TR to
w
1 Guardband
C.R.
ns
t
RSWIDTH
Reset Pulse (RS) Width
C.R.
ns
t
RS
Falling Edge of
w
1 to RS
Either Edge of
w
1 to RS
Standard CCD Mode
Even/Odd CCD Mode
C.R.
ns
t
S/HREF
Falling Edge of
w
1 to Ref. Sample
Either Edge of
w
1 to Ref. Sample
Standard CCD Mode
Even/Odd CCD Mode
C.R.
ns
t
S/HSIG
Falling Edge of
w
1 to Sig. Sample
Either Edge of
w
1 to Sig. Sample
Standard CCD Mode
Even/Odd CCD Mode
C.R.
ns
t
S/HWIDTH
Sample Pulse Width
(Acquisition Time)
50 ns
1
t
MCLK
t
SYNCLOW
SYNC Low Between Lines
100 ns
2
t
MCLK
(min)
t
B
SYNC Setup of
w
1 to End Line
2
t
MCLK
(max)
t
CCLKWIDTH
CCLK Pulse Width
250 ns
5
t
MCLK
t
DATAVALID
Data Valid Time from EOC Low
300
ns (min)
t
EOCWIDTH
EOC Pulse Width
250 ns
5
t
MCLK
w
1 and
w
2 Frequency
Standard CCD Mode
Even/Odd CCD Mode
2.5 MHz
1.25 MHz
f
MCLK
/
8
f
MCLK
/
16
Hz
Hz
w
1 and
w
2 Duty Cycle
50
%
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