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參數(shù)資料
| 型號(hào)： | LM9810 |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | LM9810/20 10/12-Bit Image Sensor Processor Analog Front End |
| 中文描述： | LM9810/20 10/12-Bit圖像傳感器模擬前端處理器 |
| 文件頁數(shù)： | 6/21頁 |
| 文件大?。?/td> | 148K |
| 代理商： | LM9810 |
6
http://www.national.com
Note 1:
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional,
but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed specifications apply
only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions.
Note 2:
All voltages are measured with respect to GND=
AGND
=
DGND
=0V, unless otherwise specified.
Note 3:
When the input voltage (V
) at any pin exceeds the power supplies (V
<GND or V
>VA or VD), the current at that pin should be limited to 25mA. The 50mA
maximum package input current rating limits the number of pins that can simultaneously safely exceed the power supplies with an input current of 25mA to two.
Note 4:
The maximum power dissipation must be derated at elevated temperatures and is dictated by T
max,
Θ
and the ambient temperature, T
. The maximum allow-
able power dissipation at any temperature is P
D
= (T
J
max - T
A
) /
Θ
JA
. T
J
max = 150°C for this device. The typical thermal resistance (
Θ
JA
) of this part when board mounted
is 84°C/W for the M20B SOIC package
.
Note 5:
Human body model, 100pF capacitor discharged through a 1.5k
resistor.
Note 6:
See AN450 “Surface Mounting Methods and Their Effect on Product Reliability” or the section titled “Surface Mount” found in any National Semiconductor Linear
Data Book for other methods of soldering surface mount devices.
AC Electrical Characteristics
The following specifications apply for
AGND
=
DGND
=0V,
VA
=
VD
=+5.0V
DC
,
f
MCLK
=24MHz
,
t
MCLK
=1/f
M
CLK
,
t
r
=t
f
=5ns, R
s
=25
.
Boldface
limits apply for T
A
=T
J
=T
MIN
to T
MAX
; all other limits T
A
=T
J
=25°C. (Notes 7 & 8)
Symbol
Parameter
Conditions
Typical
(Note 9)
Limits
(Note 10)
Units
(Limits)
f
MCLK
Maximum
MCLK
Frequency
24
MHz (min)
MCLK
Duty Cycle
40
60
% (min)
% (max)
t
MCLK
MCLK
period
41
ns (min)
t
SCNL
SampCLK
falling edge before
NewLine
falling edge
3
t
MCLK
(min)
t
SampCLK
SampCLK
period
4
t
MCLK
(min)
t
SampLo
Low time for
SampCLK
50
ns (min)
t
SampHi
High time for
SampCLK
50
ns (min)
t
SampSU
SampCLK
falling edge before rising
edge of
MCLK
4
ns (min)
t
DDO
falling edge of
MCLK
before new valid
data
40
ns (max)
t
HDO
hold time of current data from falling
edge of
MCLK
15
ns (min)
t
SCLK
D2
(SCLK) Serial Clock Period
1
t
MCLK
(min)
t
DSU
Input data setup time before
D2
(SCLK) rising edge
0
ns (min)
t
DH
Input data hold time after
D2
(SCLK)
rising edge
3
ns (min)
t
SCLKLA
D2
(SCLK) rising edge after bit B0
before
D1
(Latch) rising edge
3
ns (min)
t
LASCLK
D1
(Latch) rising edge before next
D2
(SCLK) rising edge
3
ns (min)
t
LA
High time for
D1
(Latch)
3
t
MCLK
(min)
t
LANL
D1
(Latch) rising edge before
NewLine
falling edge
3
t
SampCLK
(min)
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