參數(shù)資料
型號: LM9823CCWMX
廠商: NATIONAL SEMICONDUCTOR CORP
元件分類: 模擬信號調理
英文描述: LM9823 3 Channel 48-Bit Color Scanner Analog Front End
中文描述: SPECIALTY ANALOG CIRCUIT, PDSO28
封裝: 0.300 INCH, PLASTIC, SOIC-28
文件頁數(shù): 17/22頁
文件大?。?/td> 244K
代理商: LM9823CCWMX
17
www.national.com
Applications Information
1.0 Introduction
The LM9823 is a high performance scanner Analog Font End
(AFE) for image sensor processing systems. It is designed to
work with color CCD and CIS image sensors and provides a full 3
channel sampling, gain and offset correction system, coupled
with a 16 bit high speed analog to digital converter. A typical
application of the LM9823 is in a color flatbed document scanner.
The image sensing and processing portion of the system would
be configured similar to that shown in Figure 1.
Figure 1. LM9823 in Basic Color Scanner
2.0 CDS Correlated Double Sampler
The LM9823 uses a high-performance CDS (Correlated Double
Sampling) circuit to remove many sources of noise and error from
the image sensor output signal. It also supports CIS image sen-
sors with a single ended sampling mode.
Figure 2 shows the output stage of a typical CCD and the result-
ing output waveform:
Figure 2. CDS
Capacitor C1 converts the electrons coming from the CCD’s shift
register to an analog voltage. The source follower output stage
(Q2) buffers this voltage before it leaves the CCD. Q1 resets the
voltage across capacitor C1 between pixels at intervals 2 and 5.
When Q1 is on, the output signal (OS) is at its most positive volt-
age. After Q1 turns off (period 3), the OS level represents the
residual voltage across C1 (V
RESIDUAL
). V
RESIDUAL
includes
charge injection from Q1, thermal noise from the ON resistance
of Q1, and other sources of error. When the shift register clock
(1) makes a low to high transition (period 4), the electrons from
the next pixel flow into C1. The charge across C1 now contains
the voltage proportional to the number of electrons plus V
, an error term. If OS is sampled at the end of period 3 and
that voltage is subtracted from the OS at the end of period 4, the
V
term is canceled and the noise on the signal is
reduced ([V
+V
]-V
= V
SIGNAL
). This is the
principal of Correlated Double Sampling.
3.0 CIS Mode (CDS Off, Selectable Signal Polarity)
The also LM9823 supports CIS (Contact Image Sensor) devices.
The output signal of a CIS sensor (Figure 3) differs from a CCD
signal in two primary ways: its output usually increases with
increasing signal strength, and it does not usually have a refer-
ence level as an integral part of the output waveform of every
pixel.
Figure 3. CIS
When the LM9823 is in CIS (CDS off) mode (Register 0, B5=1), it
uses either V
or V
as the reference (or black) voltage for
each pixel (depending on the signal polarity setting (Register 0,
Bit 4)). If the signal polarity is set to one, then V
will be sam-
pled as the reference level. If it is set to zero, then V
REF+
will be
sampled as the reference level.
4.0 Programmable Gain
The output of the Sampler drives the input of the x3 Boost gain
stage. The gain of each x3 Boost gain is 3V/V if bit B5 of that
color’s gain register (register 4,5, or 6) is set, or 1V/V if bit B5 is
cleared. The output of each x3 gain stage is the input an offset
DAC and the output of each offset DAC is the input to a PGA
(Programmable Gain Amplifier). Each PGA provides 5 bits of gain
correction over a 0.93V/V to 3V/V (-0.6 to 9.5dB) range. The x3
Boost gain stage and the PGA can be combined for an overall
gain range of 0.93V/V to 9.0V/V (-.6 to 19dB). The gain setting for
each color (registers 4, 5 and 6) should be set during calibration
to bring the maximum amplitude of the strongest pixel to a level
just below the desired maximum output from the ADC. The PGA
gain is determined by the following equation:
PGA Gain V
V
Equation 1. PGA Gain
If the x3 Boost gain is enabled then the overall signal gain will be
three times the PGA gain.
ASIC
L
C
RAM
8 Output Data
8
OS
R
OS
G
OS
B
CCD Control
AFE Control
To Host
Other scanner elements
omitted for simplicity.
RS (RESET)
e-
(from shift register)
OS
Q1
Q2
C1
V
DD
V
SS
1
RS
OS
1
2
3
4
5
OS (CCD)
1
2
3
4
5
OS (CIS)
0.933 + .0667 (value in bits B4-B0)
=
L
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