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Note 1:
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional,
but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed specifications apply
only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions.
Note 2:
All voltages are measured with respect to GND=AGND=DGND=DGND
I/O
=DGND
SRAM
=0V, unless otherwise specified.
Note 3:
When the input voltage (V
) at any pin exceeds the power supplies (V
<GND or V
>V
or V
), the current at that pin should be limited to 25mA. The 50mA max-
imum package input current rating limits the number of pins that can simultaneously safely exceed the power supplies with an input current of 25mA to two.
Note 4:
The maximum power dissipation must be derated at elevated temperatures and is dictated by T
max,
Θ
and the ambient temperature, T
. The maximum allow-
able power dissipation at any temperature is P
D
= (T
J
max - T
A
) /
Θ
JA
. T
J
max = 150°C for this device. The typical thermal resistance (
Θ
JA
) of this part when board mounted
is 53°C/W
.
Note 5:
Human body model, 100pF capacitor discharged through a 1.5k
resistor.
Note 6:
See AN450 “Surface Mounting Methods and Their Effect on Product Reliability” or the section titled “Surface Mount” found in any National Semiconductor Linear
Data Book for other methods of soldering surface mount devices.
Note 7:
Two diodes clamp the OS analog inputs to
AGND
and
VA
as shown below. This input protection, in combination with the external clamp capacitor and the output
impedance of the sensor, prevents damage to the LM9830 from transients during power-up.
Note 8:
For best performance, it is required that all supply pins be powered from the same power supply with separate bypass capacitors at each supply pin.
Note 9:
Typicals are at T
J
=T
A
=25°C, f
CRYSTAL IN
= 50MHz, and represent most likely parametric norm.
Note 10:
Tested limits are guaranteed to National's AOQL (Average Outgoing Quality Level).
Note 11:
Integral linearity error is defined as the deviation of the analog value, expressed in LSBs, from the straight line that best fits the actual transfer function of the ADC.
Note 12:
V
is defined as the CCD OS voltage for the reference period following the reset feedthrough pulse. V
is defined as the peak CCD pixel output voltage for
a white (full scale) image with respect to the reference level, V
.
V
is defined as the peak positive deviation above V
of the reset feedthrough pulse. The maximum
correctable range of pixel-to-pixel V
WHITE
variation is defined as the maximum variation in V
WHITE
(due to PRNU, light source intensity variation, optics, etc.) that the
SRAM Write Timing (Figure 8) - Typical Values Represent Worst Case Timing for Different MCLK Frequencies
t
WR F ADDR
SETUP
Address valid to WR falling
0.5 t
MCLK
- 7ns
3
ns (min)
t
WR R ADDR
SETUP
Address valid to WR rising
1.5 t
MCLK
- 9ns
21
ns (min)
t
WR DATA SETUP
DB0-DB7 valid to WR rising
1 t
MCLK
- 9ns
11
ns (min)
t
WR
WR pulse width
1 t
MCLK
- 5ns
15
ns (min)
t
WR ADDR HOLD
WR rising to Address data change
0.33 t
MCLK
- 4ns
2
ns (min)
t
WR DATA HOLD
WR rising to DB0-DB7 data Tri-State
1
4
ns (max)
SRAM Read Timing (Figure 9) - Typical Values Represent Worst Case Timing for Different MCLK Frequencies
t
RD SETUP
Address valid to DB0-DB7 data valid
4 slot mode
2 t
MCLK
- 12ns
28
ns (max)
8 slot mode
(f
MCLK
= 25MHz)
1 t
MCLK
- 12ns
AC Electrical Characteristics
The following specifications apply for AGND=DGND=DGND
I/O
=DGND
SRAM
=0V, V
A
=V
D
=V
DI/O
=V
SRAM
=+5.0V
DC
,
f
CRYSTAL IN
= 50MHz, MCLK DIVIDER = 1.0 (unless otherwise noted), f
MCLK
= f
CRYSTAL IN
/MCLK DIVIDER, f
ADC CLK
= f
MCLK
/8,
C
L
(databus loading) = 20pF/pin.
Boldface limits apply for T
A
=T
J
=T
MIN
to T
MAX
; all other limits T
A
=T
J
=25°C. (Notes 7 & 8)
Symbol
Parameter
Conditions
Typical
(Note 9)
Limits
(Note 10)
Units
(Limits)
OS Input
AGND
VA
To Internal
Circuitry