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參數(shù)資料
| 型號： | LM9830VJDX |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 消費家電 |
| 英文描述： | LM9830 36-Bit Color Document Scanner |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP100 |
| 封裝： | PLASTIC, TQFP-100 |
| 文件頁數(shù)： | 9/45頁 |
| 文件大?。?/td> | 566K |
| 代理商： | LM9830VJDX |
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Figure 5: μP Mode Address Latch
CS (INIT)
RD (AUTOFEED)
Address
D0 - D7
WR (STROBE)
ALE (SELECTIN)
t
ALE SETUP
t
ALE
t
ALE HOLD
Data
Figure 6: μP Mode Write
CS (INIT)
RD (AUTOFEED)
D0 - D7
WR (STROBE)
ALE (SELECTIN)
t
WR SETUP
t
WR HOLD
t
WR
NOTE: CS and WR are ORed together.
t
and t
refer to the first rising edge
of CS or WR, whichever goes high first.
Data
Figure 7: μP Mode Read
CS (INIT)
RD (AUTOFEED)
D0 - D7
WR (STROBE)
ALE (SELECTIN)
t
RD ACCESS
t
RD TRI-STATE
NOTE: CS and RD are ORed together.
t
RD ACCESS
begins when both CS and WR go low.
t
RD TRI-STATE
begins when either CS or WR go high
Figure 8: SRAM Write
WR
Address
Data
t
WR DATA HOLD
A0-A17
DB0-DB7
t
WR ADDR HOLD
t
WR DATA SETUP
t
WR
t
WR R ADDR SETUP
t
WR F ADDR SETUP
Figure 9: SRAM Read
RD
Address
Data
A0-A17
DB0-DB7
Note: RD will stay low during consecutive read operations.
Address
Data
0.5MCLK
0.5MCLK
t
RD SETUP
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