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參數(shù)資料
| 型號： | LM98501 |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | 10-Bit, 27 MSPS Camera Signal Processor |
| 中文描述： | 10位，27 MSPS的攝像機信號處理器 |
| 文件頁數(shù)： | 15/24頁 |
| 文件大?。?/td> | 490K |
| 代理商： | LM98501 |
System Overview
(Continued)
ANALOG CLAMP
During optical black pixels, an offset often appears on the
CCD generated input signal. This offset may be seen by the
CDS circuitry as a valid video signal rather than the actual
black level signal; therefore, the LM98501 provides an ana-
log clamp designed to eliminate this offset during black pix-
els. Pulsing the analog input pin, ACLP, causes the output of
the CDS to be sampled by the analog clamp circuitry. Subse-
quently, an adjustment is made to the CDS reference volt-
ages by the analog clamp to effectively eliminate any offset
present in the signal during black pixels.
10-BIT ANALOG-TO-DIGITAL CONVERTER
The selected imager’s analog signal is sampled by the CDS
and amplified to match the input requirements of the 10-bit
analog-to-digital converter by the PGA. The final step per-
formed by the system is to convert the selected analog im-
age to digital values with a 10 bits of resolution. The ADC
has differential inputs and outputs (internally) which aids in
the coping with headroom constraints common to +3V sys-
tems. Data is acquired at the falling edge of the clock and is
available at the digital output pins 7.0 clock cycles plus t
OD
later.
INTERNAL VOLTAGE REFERENCE
An on-board, temperature stable voltage reference is em-
ployed based on a differential, continuous-time bandgap cir-
cuit. The employment of this on-chip reference eliminates
the need for external reference drive circuitry and compo-
nents, minimizing cost and board space in a design. The use
of external bypass capacitors from the reference pins to
ground is recommended for reducing reference drive re-
quirements, resulting in reduced power dissipation.Asecond
on-chip reference is used exclusively for the offset DAC and
follows the same procedures for bypassing with external ca-
pacitors.
INTERNAL TIMING GENERATION
All if the necessary clocks for the CDS and ADC operation
are generated internally from the LM98501’s master clock in-
put. The CDS sampling clocks may be overridden by the
user via the SHP and SHD clock inputs. As depicted in Fig-
ure 4and Figure 5 there are two signals generated internally
for CDS sampling referred to as CLAMP and SAMPLE.
These signals provide the rising edge reference for the sam-
pling of the CCD input signal. The timing of CLAMP and
SAMPLE is derived from the clock; therefore, shifting the
clock phasing with respect to the CCD input signal would
also shift the rising (and falling) edges of CLAMP and
SAMPLE. The actual sampling of the CCD’s reset voltage
and video signal is performed on the falling edges of the
CLAMP and SAMPLE signals respectively. The user may
modify the position of the falling edges where the sampling
of the CCD input occurs by driving the SHP and SHD inputs
of the LM98501. The falling edges of SHP and SHD will su-
persede the falling edges of CLAMP and SAMPLE respec-
tively and cause the duration of the sample pulse to shorten
accordingly. As evidenced in Figure 4 and Figure 5 the fall-
ing edges of SHP and SHD should not occur earlier than
t
or t
after the respective falling [SHP] (or rising
[SHD]) edge of CLK.
SERIAL INTERFACE AND CONFIGURATION
REGISTERS
There are many options available to the user that may be
programmed via the LM98501’s serial interface. Configura-
tion values are stored in registers for use by several func-
tions such as programmable gain, offset, black level, and
color filter array.
The LM98501’s serial interface is used to store values into
16 8-bit configuration registers. Upon power-up or external
reset, the configuration registers will contain their respective
default values. Default values place the LM98501 in ‘single
channel’ mode, where only one PGA gain and offset are ap-
plied to the input signal.
The master CLK input is required to be running during serial
interface commands. Each command issued through the se-
rial interface must have a minimum of 13 data bits (see Fig-
ures 13, 14).
PGA GAIN
The four PGA gain registers store four possible gain values
for the programmable gain amplifier (PGA). For example,
these four gain values may correspond to four possible col-
ors in a color filter array.
ANALOG OFFSET
The analog offset registers store four possible values that
correspond to the four gain values. For example, the value
stored in the PGAgain register 0 (address 0h) is used in con-
junction with the offset value stored in the analog offset reg-
ister 0 (address 4h). This allows for four possible combina-
tions of PGA gain and analog offset, one for each color filter.
These registers are read-only when offset auto-calibration is
enabled in the software control register 0. It should be noted
that each offset DAC step (1 LSB) corresponds to a 0.4 LSB
step at the ADC output. Therefore, if an offset of 20 digital
codes is desired at theADC output, a digital code value of 50
should be stored in the analog offset register(s). As a result,
the maximum offset seen at the ADC output as a result of
digital code values stored in the analog offset register(s) is
±
54 codes. It is possible to increase the digital output range
of the analog offset DAC, resulting in a increased maximum
ADC output code corresponding to a given DAC input. for
more information on increasing the DAC range, please see
ANALOG OFFSET DAC RANGE ADJUSTMENT
OUTPUT BLACK LEVEL
The output black level register is occupied by an 8-bit word
stored by the user that specifies the output level correspond-
ing to optical black. For example, a user that wants an output
level of 16 for black pixels must write this value into the reg-
ister during the horizontal interval. Once this has been ac-
complished, driving the BLKCLP high for 20 cycles of CLK
activates the digital black clamp loop and the black level is
forced to the value stored in the output black level register, in
the example case the code value of 16. As a result of the re-
lationship between the DAC input and the ADC output (see
’Analog Offset’), the largest output black level code the
LM98501 is capable of clamping to is 54 codes.
L
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| LM98501A WAF | 制造商:Texas Instruments 功能描述: |
| LM98501CCVBH | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:10-Bit, 27 MSPS Camera Signal Processor |
| LM98501VBH WAF | 制造商:Texas Instruments 功能描述: |
| LM98502A WAF | 制造商:Texas Instruments 功能描述: |
| LM98503 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:10-Bit, 18 MSPS Camera Signal Processor |
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