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參數(shù)資料
| 型號： | LM98503 |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | 10-Bit, 18 MSPS Camera Signal Processor |
| 中文描述： | 10位，18 MSPS的攝像機信號處理器 |
| 文件頁數(shù)： | 17/25頁 |
| 文件大小： | 203K |
| 代理商： | LM98503 |
www.national.com
17
Register Memory Map
Title
Address
Default Value
PGA Gain 0
0000
0000 0000 (0d)
PGA Gain 1
0001
0000 0000 (0d)
PGA Gain 2
0010
0000 0000 (0d)
PGA Gain 3
0011
0000 0000 (0d)
Analog Offset 0
0100
0000 0000 (0d)
Analog Offset 1
0101
0000 0000 (0d)
Analog Offset 2
0110
0000 0000 (0d)
Analog Offset 3
0111
0000 0000 (0d)
CFA Configuration 0
1000
0000 0000 (0d)
CFA Configuration 1
1001
0000 0000 (0d)
CFA Definition
1010
XXXX 0000 (0d)
Output Black Level
1011
0001 0000 (32d)
Software Control 0
1100
0100 1110 (78d)
Software Control 1
1101
XX00 0X00 (0d)
Power Level Control 0
1110
1010 1010 (170d)
Power Level Control 1
1111
0101 1010 (90d)
Register Data
The following section describes all available registers in the
LM98503 register bank and their functions.
2.0 PGA Gain Registers
Register Name PGA Gain 0
Address
Type
Reset Value
0 Hex
Read/Write
0000 0000 Binary
Register Name PGA Gain 1
Address
Type
Reset Value
1 Hex
Read/Write
0000 0000 Binary.Register NamePGA Gain
2
2 Hex
Read/Write
0000 0000 Binary
Address
Type
Reset Value
Register Name PGA Gain 3
Address
Type
Reset Value
3 Hex
Read/Write
0000 0000 Binary
3.0 Analog Offset Registers
Register Name Analog Offset 0
Address
Type:
Reset Value
4 Hex
Read/Write
0000 0000 Binary
Bit
Bit Symbol
Description
[7:0]
PGA Gain
0.0dB - 32.0dB in 0.125dB
steps.
Bit
Bit Symbol
Description
[7:0]
PGA Gain
0.0dB - 32.0dB in 0.125dB
steps.
Bit
Bit Symbol
Description
[7:0]
PGA Gain
0.0dB - 32.0dB in 0.125dB
steps.
Bit
Bit Symbol
Description
[7:0]
PGA Gain
0.0dB - 32.0dB in 0.125dB
steps.
Bit
Bit Symbol
Description
[7:0]
Signed Analog
Offset
Digital representation of the
analog offset to be applied to
the input of the PGA. See
“Analog Offset” on page 15.
L
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| LM98503CCVV | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:10-Bit, 18 MSPS Camera Signal Processor |
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