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參數(shù)資料
| 型號(hào)： | LMC2626 |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | CMOS LDOR/Buffer Chip for Row Inversion Flat Panel Display Systems |
| 中文描述： | 的CMOS LDOR /緩沖器芯片的行反轉(zhuǎn)平板顯示系統(tǒng) |
| 文件頁數(shù)： | 4/6頁 |
| 文件大?。?/td> | 92K |
| 代理商： | LMC2626 |
AC Electrical Characteristics
Unless otherwise specified, all limits guaranteed for T
A
e
27
§
C, V
IN
e e
P5V
e
5V. Other conditions are shown in the test
circuit. Conditions that deviate from those shown in the test circuit are listed in the conditions column.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
(Note 9)
t
s(OUT)
Settling Time for V
OUT
To 98% p-p V
OUT
,
V
IN
e
5V (see Note 3)
5.0
m
s
Note 1:
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating ratings indicate conditions the device is intended
to be functional, but device parameter specifications may not be guaranteed under these conditions. For guaranteed specifications and test conditions, see
the Electrical Characteristics.
Note 2:
The typical junction-ambient thermal resistance of the molded plastic SO(M) package is 155
§
C/W. Therefore the maximum current for the buffer and
voltage regulator are limited to the maximum total power dissipation that the package can allow in order to keep the die comfortably below the maximum
operating junction temperature of 125
§
C.
Note 3:
The settling time of the Power Buffer is mostly dependent upon the TFT effective series RC load. The measurement of the settling time is taken for the
application when driving an all black display. The number in the datasheet reflects a series RC load (R
e
6.8
X
and C
e
0.22
m
F).
Note 4:
Human Body Model 100 pF and 1.5 k
X
. Machine Model 0
X
.
Note 5:
The precision of the P5V supply determines the output voltage swing precision of the buffer for very small loads. The operating range of P5V in this
datasheet assumes a
g
4% error in V
OUT
p-p such that the total error of the signal at the output of the buffer never exceeds
g
5%.
Note 6:
This capacitance is dominated by the ESD protection zeners connected to the SYNC pin.
Note 7:
It is important to understand that the load current of the low drop-out voltage regulator must not drop below 2 mA. Otherwise, the internal error
amplifier will not have sufficient drive capability to the large series pass transistor. If load requirements from the FPD system is less than 2 mA, an external pre-
Ioad resistor must be connected from V
SH
to ground in order to satisfy the previously mentioned load requirements.
Note 8:
The thermal shutdown mode of the voltage regulator and the system shutdown mode are identical. When either of the two functions are enabled, two
results occur. The pass transistor of the voltage regulator is shut off and The V
REF
pin of the LMC2626 is pulled up to the V
IN
supply to shutdown the LM2625
switching regulator.
Note 9:
Typical values represent the most likely parametric norm.
Note 10:
The typical closed loop voltage gain of the low drop-out voltage regulator is 3.44(10.7 dB).
Note 11:
The minimum load current of the voltage regulator is a specific parameter used to guarantee that the regulated output voltage of the LDO regulator
stays within the limits specified in the datasheet for 1.216V
k
V
REF
k
1.242V. For applications requiring minimum load current less than 20 mA, regulated
output voltage limits of the voltage regulator and V
REF
voltage range must be carefully determined by characterizing the change in regulated output voltage at
the minimum load current needed.
4
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