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參數(shù)資料
| 型號(hào)： | LMC2626IM |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 模擬信號(hào)調(diào)理 |
| 英文描述： | CMOS LDOR/Buffer Chip for Row Inversion Flat Panel Display Systems |
| 中文描述： | SPECIALTY ANALOG CIRCUIT, PDSO8 |
| 封裝： | 0.150 INCH, PLASTIC, SOP-8 |
| 文件頁數(shù)： | 3/6頁 |
| 文件大?。?/td> | 92K |
| 代理商： | LMC2626IM |
DC Electrical Characteristics
Unless otherwise specified, all limits guaranteed for
b
20
§
C
s
T
A
s
a
85
§
C, P5V
e
5V and 4.5V
s
V
IN
s
5.5V, V
REF
e
1.227V
SYNC(OPEN), SD(OPEN)
k
P5V
e
V
IN
e
5V (Continued)
Buffer
Symbol
Parameter
Conditions
Min
Typ
Max
Units
(Note 9)
V
OUT
Peak to Peak Output
Voltage Swing or V
OUT
SYNC
e
5V
pp
(no load)
4.997
4.999
V
V
OL
Low Level Output
Voltage
SYNC
e
0V
(No Load)
0.2
2
mV
V
OH
High Level Output
Voltage
SYNC
e
5V
(No Load)
4.999
V
D
VOUT
Variation of V
OUT
Over Temperature
0.2
1
3
mV
V
IH
SYNC, SD
High Level Input
Voltage
3.5
5
V
V
IL
SYNC, SD
Low Level Input
Voltage
0
1.5
V
I
IL(SYNC)
Low Level Input
Current for SYNC
SYNC
e
0V
5.0
42
1000
nA
I
IH(SYNC)
High Level Input
Current for SYNC
SYNC
e
5V
DC
170
215
275
m
A
I
OUT-AVE
V
OUT
Maximum Average
Load Current from (see Note 2)
SYNC
e
5V
PP
100
mA
R
ON
N-Channel
On Resistance
IL
e
150 mA
T
A
e
27
§
C
0.9
1.5
X
R
ON
P-Channel
On Resistance
IL
e
150 mA
T
A
e
27
§
C
0.7
1.2
X
R
ON
Matching
On Resistance
IL
e
150 mA
T
A
e
27
§
C
0.18
0.6
X
I
s
Supply Current
from P5V
No SYNC
200
355
950
m
A
3
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