參數(shù)資料
型號: LMH6572MQ
廠商: NATIONAL SEMICONDUCTOR CORP
元件分類: 多路復(fù)用及模擬開關(guān)
英文描述: Triple 2:1 High Speed Video Multiplexer
中文描述: TRIPLE 2-CHANNEL, VIDEO MULTIPLEXER, PDSO16
封裝: SSOP-16
文件頁數(shù): 2/12頁
文件大?。?/td> 409K
代理商: LMH6572MQ
Absolute Maximum Ratings
(Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
ESD Tolerance
Human Body Model
Machine Model
Supply Voltage (V
+
V
)
I
OUT
(Note 3)
IInput Voltage Range
Maximum Junction Temperature
Storage Temperature Range
±
5V Electrical Characteristics
V
S
=
±
5V, R
L
= 100
, Unless otherwise specified.
Symbol
Parameter
Frequency Domain Performance
SSBW
3 dB Bandwidth
LSBW
–3 dB Bandwidth (Note 6)
.1 dBBW
. 1 dB Bandwidth
DG
Differential Gain
DP
Differential Phase
Time Domain Response
TRS
Channel to Channel Switching Time
Enable and Disable Times
(Note 4)
2000V
200V
13.2V
130 mA
±
V
S
+150C (Note 4)
65C to +150C
Soldering Information
Infrared or Convection (20 sec)
Wave Soldering (10 sec)
235C
260C
Operating Ratings
(Note 1)
Operating Temperature
Supply Voltage Range
Thermal Resistance
Package
16-Pin SSOP
40C
6V
to
to
85C
12V
(
θ
JA
)
125C/W
(
θ
JC
)
36C/W
Conditions
(Note 2)
Min
Typ
Max
Units
V
OUT
= 0.25 V
PP
V
OUT
= 2 V
PP
V
OUT
= 0.25 V
PP
R
L
= 150
, f=4.43 MHz
R
L
= 150
, f=4.43 MHz
350
290
140
0.02
0.02
MHz
MHz
MHz
%
deg
250
Logic transition to 90% output
Logic transition to 90% or 10%
output.
2V Step
2V Step
4V Step
4V Step
10
11
ns
ns
TRL
TSS
OS
SR
Distortion
HD2
HD3
IMD
Equivalent Input Noise
VN
Voltage
ICN
Current
Static, DC Performance
GAIN
Voltage Gain (Note 5)
Gain Error(Note 5)
Rise and Fall Time
Settling Time to 0.05%
Overshoot
Slew Rate(Note 6)
1.5
17
5
1400
ns
ns
%
V/μs
1200
2
nd
Harmonic Distortion
3
rd
Harmonic Distortion
3
rd
Order Intermodulation Products
2 V
PP
, 10 MHz
2 V
PP
, 10 MHz
10 MHz, Two tones 2Vpp at output
78
75
80
dBc
dBc
dBc
>
1 MHz, Input Referred
>
1 MHz, Input Referred
5
5
nV
pA/
No Load
No Load, channel to channel
1.9
2.0
±
0.3
2.1
±
0.5
±
0.7
V/V
%
Gain Error
Output Offset Voltage (Note 5)
R
L
= 50
V
IN
= 0V
0.3
1
%
mV
VIO
±
14
±
17.5
DVIO
IBN
Average Drift
Input Bias Current (Notes 7, 5)
27
1.4
μV/C
μA
V
IN
= 0V
±
2.8
±
3.5
DIBN
PSRR
Average Drift
Power Supply Rejection Ratio
(Note 5)
7
54
nA/C
dB
DC, Input referred
50
48
L
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