DATA SHEET
LMV321/LMV358/LMV324
4
REV. 1D. Feb. 2012
Electrical Specifications
(Tc = 25°C, Vs = +5V, G = 2, RL = 10k to Vs/2, Rf = 10k, Vo (DC) = Vcc/2; unless otherwise noted)
Parameter
Conditions
Min.
Typ.
Max.
Unit
AC Performance
Gain Bandwidth Product
CL = 50pF, RL =2k to Vs/2
1.4
MHz
Phase Margin
73
deg
Gain Margin
12
dB
Slew Rate
1.5
V/
s
Input Voltage Noise
>50kHz
33
nV/
√Hz
Crosstalk: LMV358
100kHz
91
dB
LMV324
100kHz
80
dB
DC Performance
Input Offset Voltage1
17
mV
Average Drift
6
V/°C
Input Bias Current2
<1
nA
Input Offset Current2
<1
nA
Power Supply Rejection Ratio1
DC
50
65
dB
Open Loop Gain1
50
70
dB
Supply Current (Per Channel)1
100
150
A
Input Characteristics
Input Common Mode Voltage Range1 LO
0
-0.4
V
HI
3.8
3.6
V
Common Mode Rejection Ratio1
50
75
dB
Output Characteristics
Output Voltage Swing
RL = 2k to Vs/2; LO/HI
0.036 to 4.95
V
RL = 10k to Vs/2; LO1
0.1
0.013
V
RL = 10k to Vs/2; HI1
4.98
4.9
V
Short Circuit Output Current1
sourcing; Vo = 0V
5
+34
mA
sinking; Vo = 5V
10
-23
mA
Min/max ratings are based on product characterization and simulation. Individual parameters are tested as noted. Outgoing quality levels are
determined from tested parameters.
Notes:
1. Guaranteed by testing or statistical analysis at +25°C.
2. +IN and -IN are gates to CMOS transistors with typical input bias current of <1nA. CMOS leakage is too small to practically measure.
Package Thermal Resistance
Package
θ
JA
5 lead SC70
331.4°C/W
5 lead SOT23
256°C/W
8 lead SOIC
152°C/W
8 lead MSOP
206°C/W
14 lead SOIC
88°C/W