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參數(shù)資料
| 型號： | LMX2326SLBX/NOPB |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | PLL合成/DDS/VCOs |
| 英文描述： | PLL FREQUENCY SYNTHESIZER, 2800 MHz, CQCC16 |
| 封裝： | CSP-16 |
| 文件頁數(shù)： | 12/19頁 |
| 文件大小： | 301K |
| 代理商： | LMX2326SLBX/NOPB |
Connection Diagrams
Pin Descriptions
16-Pin
TSSOP
16-Pin
CSP
Pin
Name
I/O
Description
115
FL
o
O
FastLock Output. For connection of parallel resistor to the loop filter. (See Section 1.3.4
FASTLOCK MODES description.)
216
CP
o
O
Charge Pump Output. For connection to a loop filter for driving the input of an external VCO.
3
1
GND
Charge Pump Ground.
4
2
GND
Analog Ground.
53
f
IN
I
RF Prescaler Complementary Input. A bypass capacitor should be placed as close as possible to
this pin and be connected directly to the ground plane. The complementary input can be left
unbypassed, with some degradation in RF sensitivity.
64
f
IN
I
RF Prescaler Input. Small signal input from the VCO.
75
V
CC1
Analog Power Supply Voltage Input. Input may range from 2.3V to 5.5V. Bypass capacitors should
be placed as close as possible to this pin and be connected directly to the ground plane. V
CC1
must equal V
CC2.
8
6
OSC
IN
I
Oscillator Input. This input is a CMOS input with a threshold of approximately V
CC/2 and an
equivalent 100k input resistance. The oscillator input is driven from a reference oscillator.
9
7
GND
Digital Ground.
10
8
CE
I
Chip Enable. A LOW on CE powers down the device and will TRI-STATE the charge pump output.
Taking CE HIGH will power up the device depending on the status of the power down bit F2. (See
Section 1.3.1 POWERDOWN OPERATION and Section 1.7.1 DEVICE PROGRAMMING AFTER
FIRST APPLYING V
CC.)
11
9
Clock
I
High Impedance CMOS Clock Input. Data for the various counters is clocked in on the rising edge
into the 21-bit shift register.
12
10
Data
I
Binary Serial Data Input. Data entered MSB first. The last two bits are the control bits. High
impedance CMOS input.
13
11
LE
I
Load Enable CMOS Input. When LE goes HIGH, data stored in the shift registers is loaded into one
of the 3 appropriate latches (control bit dependent).
14
12
Fo/LD
O
Multiplexed Output of the RF Programmable or Reference Dividers and Lock Detect. CMOS output.
(See
Table 4.)
15
13
V
CC2
Digital Power Supply Voltage Input. Input may range from 2.3V to 5.5V. Bypass capacitors should
be placed as close as possible to this pin and be connected directly to the ground plane. V
CC1
must equal V
CC2.
16
14
V
P
Power Supply for Charge Pump. Must be
≥ V
CC.
LMX2306/16/26
DS100127-2
16-Lead (0.173” Wide) Thin Shrink Small Outline
Package(TM)
Order Number LMX2306TM, LMX2306TMX,
LMX2316TM, LMX2316TMX,
LMX2326TM or LMX2326TMX
See NS Package Number MTC16
LMX2306/16/26
DS100127-19
16-pin Chip Scale Package
Order Number LMX2306SLBX, LMX2316SLBX or
LM2326SLBX
See NS Package Number SLB16A
LMX2306/LMX2316/LMX2326
www.national.com
2
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| LMX2326TM | 制造商:Texas Instruments 功能描述:PLL Frequency Synthesizer Single 100MHz to 2800MHz 16-Pin TSSOP Rail |
| LMX2326TM | 制造商:Texas Instruments 功能描述:2.8GHZ SINGLE PLL 2326 TSSOP16 |
| LMX2326TM/NOPB | 功能描述:IC FREQ SYNTHESIZER 16-TSSOP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:PLLatinum™ 標準包裝:39 系列:- 類型:* PLL:帶旁路 輸入:時鐘 輸出:時鐘 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:* 封裝/外殼:* 供應商設備封裝:* 包裝:* |
| LMX2326TM/NOPB | 制造商:Texas Instruments 功能描述:PHASE LOCK LOOP (PLL) IC |
| LMX2326TMD | 制造商:Texas Instruments 功能描述: |
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