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參數(shù)資料
| 型號： | LMX2352 |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | PLLatinum Fractional Dual Low Power Frequency Synthesizer(PLLatinum技術(shù)低耗雙通道頻率合成器) |
| 中文描述： | PLLatinum分?jǐn)?shù)雙低功耗頻率合成器（PLLatinum技術(shù)低耗雙通道頻率合成器） |
| 文件頁數(shù)： | 12/20頁 |
| 文件大?。?/td> | 378K |
| 代理商： | LMX2352 |
Programming Description
2.0 INPUT DATA REGISTER
The descriptions below describe the 24-bit data register loaded through the MICROWIRE Interface. The data register is used to
program the 15-bit IF_R counter register, and the 15-bit RF_R counter register, the 15-bit IF_N counter register, and the 19-bit
RF_N counter register. The data format of the 24-bit data register is shown below. The control bits CTL [1:0] decode the internal
register address. On the rising edge of LE, data stored in the shift register is loaded into one of the 4 appropriate latches (selected
by address bits). Data is shifted in MSB first
MSB
LSB
DATA [21:0]
CTL [1:0]
23
2
1
0
2.1 Register Location Truth Table
CTL [1:0]
DATA Location
1
0
0
1
1
0
0
1
0
1
IF_R register
IF_N register
RF_R register
RF_N register
2.2 Register Content Truth Table
First Bit
REGISTER BIT LOCATION
16 15 14 13 12 11 10 9 8 7 6 5
Last Bit
2
23
OSC
IF_CTL_WORD
22
21 20 19
FoLD
18
17
4
3
1 0
0 0
IF_R
IF_N
RF_R DLL_MODE
RF_N
FRAC_16
IF_CP_WORD
CMOS
RF_CP_WORD
IF_R_CNTR
IF_NB_CNTR
IF_NA_CNTR 0 1
V2_EN
RF_R_CNTR
RF_NA_CNTR
1 0
1 1
RF_CTL_WORD
RF_NB_CNTR
FRAC_CNTR
3.0 PROGRAMMABLE REFERENCE DIVIDERS
3.1 IF_R Register
If the Control Bits (CTL [1:0]) are 0 0, when LE is transitioned high data is transferred from the 24-bit shift register into a latch
which sets the IF PLL 15-bit R counter divide ratio. The divide ratio is programmed using the bits IF_R_CNTR as shown in table
3.1.3. The ratio must be
≥
3. The IF_CP_WORD [1:0], programs the IF charge pump magnitude and polarity shown in 3.1.4. The
OSC bit is used to enable the crystal oscillator mode. FoLD [2:0] is used to set the function of the Lock Detect output (pin 11),
according to table 3.1.3.
MSB
OSC
23
LSB
0
0
FRAC_16
22
FoLD [2:0]
21
IF_CP_WORD [1:0]
18
IF_R_CNTR [14:0]
16
0
1
19
17
2
3.1.1 OSC
The OSC bit, IF_R [23], selects whether the oscillator input pins OSCin and OSCx drive the IF and RF R counters separately or
by a common input signal path. When the OSC bit = 1, a crystal resonator can be connected between OSCin and OSCx together
with 2 capacitors to form a crystal oscillator. When OSC = 0 , the OSCin pin drives the IF R counter while the OSCx drives the
RF R counter.
(IF_R[23])
3.1.2 FRAC_16
The FRAC_16 bit, IF_R [22], is used to set the fractional compensation at either 1/16 and 1/15 resolution. When FRAC-16 is set
to one, the fractional modulus is set to 1/16 resolution, and FRAC_16 = 0 corresponds to 1/15 (See section 4.2.4).
(IF_R[22])
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| LMX2352SLBX | 功能描述:IC FREQ SYNTH DUAL 24LAMINATECSP RoHS:否 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:PLLatinum™ 標(biāo)準(zhǔn)包裝:39 系列:- 類型:* PLL:帶旁路 輸入:時鐘 輸出:時鐘 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:* 封裝/外殼:* 供應(yīng)商設(shè)備封裝:* 包裝:* |
| LMX2352TM | 制造商:Texas Instruments 功能描述:IC, DUAL FREQ SYNTHESIZER 1.2GHZ 24-TSSOP, PLL Type:Frequency Synthesis, Frequen |
| LMX2352TM/NOPB | 功能描述:IC FREQ SYNTHESIZER DUAL 24TSSOP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:PLLatinum™ 標(biāo)準(zhǔn)包裝:39 系列:- 類型:* PLL:帶旁路 輸入:時鐘 輸出:時鐘 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:* 封裝/外殼:* 供應(yīng)商設(shè)備封裝:* 包裝:* |
| LMX2352TMX | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Serial-Input Frequency Synthesizer |
| LMX2352TMX/NOPB | 功能描述:IC FREQUENCY SYNTHESIZER 24TSSOP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:PLLatinum™ 標(biāo)準(zhǔn)包裝:39 系列:- 類型:* PLL:帶旁路 輸入:時鐘 輸出:時鐘 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:* 封裝/外殼:* 供應(yīng)商設(shè)備封裝:* 包裝:* |
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