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參數(shù)資料
| 型號： | LMX2352TM |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | XO, clock |
| 英文描述： | CAP,CER,DISC,RAD,100PF,10%,1KV |
| 中文描述： | PLL FREQUENCY SYNTHESIZER, 1200 MHz, PDSO24 |
| 封裝： | PLASTIC, TSSOP-24 |
| 文件頁數(shù)： | 2/20頁 |
| 文件大?。?/td> | 378K |
| 代理商： | LMX2352TM |
Connection Diagram
Pin Descriptions
Pin
No.
1
2
Pin
Name
OUT0
Vcc
RF
I/O
Description
O
-
Programmable CMOS output. Level of the output is controlled by IF_N [17] bit.
RF PLL power supply voltage input. Must be equal to Vcc
IF
. May range from 2.7 V to 5.5 V.
Bypass capacitors should be placed as close as possible to this pin and be connected directly
to the ground plane.
Power supply for RF charge pump. Must be
≥
V
cc
RF
and V
cc
IF
.
RF charge pump output. Connected to a loop filter for driving the control input of an external
VCO.
Ground for RF PLL digital circuitry.
RF prescaler input. Small signal input from the VCO.
RF prescaler complimentary input. A bypass capacitor should be placed as close as possible
to this pin and be connected directly to the ground plane.
Ground for RF PLL analog circuitry.
Dual mode oscillator output or RF R counter input. Has a Vcc/2 input threshold when
configured as an input and can be driven from an external CMOS or TTL logic gate. Can also
be configured as an output to work in conjunction with OSCin to form a crystal oscillator. (See
functional description 1.1 and programming description 3.1.)
Oscillator input which can be configured to drive both the IF and RF R counter inputs or only
the IF R counter depending on the state of the OSC programming bit. (See functional
description 1.1 and programming description 3.1.)
Multiplexed output of N or R divider and RF/IF lock detect. Active High/Low CMOS output
except in analog lock detect mode. (See programming description 3.1.5.)
RF PLL Enable. Powers down RF N and R counters, prescaler, and will TRI-STATE
the
charge pump output when LOW. Bringing RF_EN high powers up RF PLL depending on the
state of RF_CTL_WORD. (See functional description 1.9.)
IF PLL Enable. Powers down IF N and R counters, prescaler, and will TRI-STATE the charge
pump output when LOW. Bringing IF_EN high powers up IF PLL depending on the state of
IF_CTL_WORD. (See functional description 1.9.)
High impedance CMOS Clock input. Data for the various counters is clocked into the 24 - bit
shift register on the rising edge.
Binary serial data input. Data entered MSB first. The last two bits are the control bits. High
impedance CMOS input.
Load enable high impedance CMOS input. Data stored in the shift registers is loaded into one
of the 4 internal latches when LE goes HIGH. (See functional description 1.7.)
3
4
V
p
RF
CP
o
RF
-
O
5
6
7
GND
fin RF
fin RF
-
I
I
8
9
GND
OSCx
-
I/O
10
OSCin
I
11
FoLD
O
12
RF_EN
I
13
IF_EN
I
14
CLOCK
I
15
DATA
I
16
LE
I
DS100831-2
Order Number LMX2350TM or LMX2352TM
NS Package Number MTC24
www.national.com
2
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| LMX2353 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:PLLatinum⑩ Fractional N Single 2.5 GHz Frequency Synthesizer |
| LMX2353SLBX | 功能描述:IC FREQ SYNTH 2.5GHZ 16LAMCSP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:PLLatinum™ 標(biāo)準(zhǔn)包裝:39 系列:- 類型:* PLL:帶旁路 輸入:時鐘 輸出:時鐘 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:* 封裝/外殼:* 供應(yīng)商設(shè)備封裝:* 包裝:* |
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