參數(shù)資料
型號(hào): LMX2485
廠商: NATIONAL SEMICONDUCTOR CORP
元件分類: XO, clock
英文描述: 50 MHz - 3.0 GHz High Performance Delta-Sigma Low Power Dual PLLatinum⑩ Frequency Synthesizers with 800 MHz Integer PLL
中文描述: PLL FREQUENCY SYNTHESIZER, 3000 MHz, PQCC24
封裝: 4 X 4 MM, 0.8 MM, PLASTIC, LLP-24
文件頁數(shù): 18/37頁
文件大?。?/td> 861K
代理商: LMX2485
Bench Test Setups
(Continued)
20087770
Frequency Input Pin
OSCin
FinRF
FinIF
OSCin
DC Blocking Capacitor
1000 pF
100 pF// 1000 pF
100 pF
1000 pF
Corresponding Counter
RF_R / 2
RF_N / 2
IF_N / 2
IF_R / 2
Default Counter Value
50
502 + 2097150 / 4194301
534
50
MUX Value
14
15
13
12
Sensitivity Measurement Procedure
Sensitivity is defined as the power level limits beyond which the output of the counter being tested is off by 1 Hz or more of its
expected value. It is typically measured over frequency, voltage, and temperature. In order to test sensitivity, the MUX[3:0] word
is programmed to the appropriate value. The counter value is then programmed to a fixed value and a frequency counter is set
to monitor the frequency of this pin. The expected frequency at the Ftest/LD pin should be the signal generator frequency divided
by twice the corresponding counter value. The factor of two comes in because the LMX2485 has a flip-flop which divides this
frequency by two to make the duty cycle 50% in order to make it easier to read with the frequency counter. The frequency counter
input impedance should be set to high impedance. In order to perform the measurement, the temperature, frequency, and voltage
is set to a fixed value and the power level of the signal is varied. Note that the power level at the part is assumed to be 4 dB less
than the signal generator power level. This accounts for 1 dB for cable losses and 3 dB for the pad. The power level range where
the frequency is correct at the Ftest/LD pin to within 1 Hz accuracy is recorded for the sensitivity limits. The temperature,
frequency, and voltage can be varied in order to produce a family of sensitivity curves. Since this is an open-loop test, the charge
pump is set to TRI-STATE and the unused side of the PLL (RF or IF) is powered down when not being tested. For this part, there
are actually four frequency input pins, although there is only one frequency test pin (Ftest/LD). The conditions specific to each pin
are shown in above table.
Note that for the RF N counter, a fourth order fractional modulator is used in 22-bit mode with a fraction of 2097150 / 4194301
is used. The reason for this long fraction is to test the RF N counter and supporting fractional circuitry as completely as possible.
L
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相關(guān)PDF資料
PDF描述
LMX2485E 50 MHz - 3.0 GHz High Performance Delta-Sigma Low Power Dual PLLatinum⑩ Frequency Synthesizers with 800 MHz Integer PLL
LMX2485ESQ 50 MHz - 3.0 GHz High Performance Delta-Sigma Low Power Dual PLLatinum⑩ Frequency Synthesizers with 800 MHz Integer PLL
LMX2485ESQX 50 MHz - 3.0 GHz High Performance Delta-Sigma Low Power Dual PLLatinum⑩ Frequency Synthesizers with 800 MHz Integer PLL
LMX2485SQ 50 MHz - 3.0 GHz High Performance Delta-Sigma Low Power Dual PLLatinum⑩ Frequency Synthesizers with 800 MHz Integer PLL
LMX2485SQX 50 MHz - 3.0 GHz High Performance Delta-Sigma Low Power Dual PLLatinum⑩ Frequency Synthesizers with 800 MHz Integer PLL
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
LMX2485_0610 制造商:NSC 制造商全稱:National Semiconductor 功能描述:50 MHz - 3.0 GHz High Performance Delta-Sigma Low Power Dual PLLatinum⑩ Frequency Synthesizers with 800 MHz Integer PLL
LMX2485_08 制造商:NSC 制造商全稱:National Semiconductor 功能描述:50 MHz - 3.0 GHz High Performance Delta-Sigma Low Power Dual PLLatinum⑩ Frequency Synthesizers with 800MHz Integer PLL
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LMX2485E 制造商:NSC 制造商全稱:National Semiconductor 功能描述:50 MHz - 3.0 GHz High Performance Delta-Sigma Low Power Dual PLLatinum? Frequency Synthesizers with 800 MHz Integer PLL
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