參數(shù)資料
型號: LMX2487SQ
廠商: NATIONAL SEMICONDUCTOR CORP
元件分類: XO, clock
英文描述: 3.0 GHz - 6.0 GHz High Performance Delta-Sigma Low Power Dual PLLatinum⑩ Frequency Synthesizers with 3.0 GHz Integer PLL
中文描述: PLL FREQUENCY SYNTHESIZER, 6000 MHz, PQCC24
封裝: 4 X 4 MM, 0.80 MM HEIGHT, PLASTIC, LLP-24
文件頁數(shù): 31/37頁
文件大?。?/td> 856K
代理商: LMX2487SQ
Programming Description
(Continued)
2.5 R4 REGISTER
This register controls the conditions for the RF PLL in Fastlock.
REGISTER
23
22 21 20 19 18 17 16 15 14 13
12
11
10
9
8
7 6 5 4
3
2
1
0
DATA[19:0]
FM
[1:0]
C3 C2 C1 C0
R4
ATPU
0
1
0
0
0
DITH
[1:0]
0
OSC_
2X
OSC_
OUT
IF_
CPP
RF_
CPP
IF_P
MUX
[3:0]
1
0
0
1
2.5.1 MUX[3:0] Frequency Out & Lock Detect MUX
These bits determine the output state of the Ftest/LD pin.
MUX[3:0]
Output Type
High Impedance
Push-Pull
Push-Pull
Push-Pull
Push-Pull
Push-Pull
Open Drain
Open Drain
Open Drain
Push-Pull
Push-Pull
Push-Pull
Push-Pull
Push-Pull
Push-Pull
Push-Pull
Output Description
Disabled
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
General purpose output, Logical “High” State
General purpose output, Logical “Low” State
RF & IF Digital Lock Detect
RF Digital Lock Detect
IF Digital Lock Detect
RF & IF Analog Lock Detect
RF Analog Lock Detect
IF Analog Lock Detect
RF & IF Analog Lock Detect
RF Analog Lock Detect
IF Analog Lock Detect
IF R Divider divided by 2
IF N Divider divided by 2
RF R Divider divided by 2
RF N Divider divided by 2
2.5.2 IF_P -- IF Prescaler
When this bit is set to 0, the 8/9 prescaler is used. Otherwise the 16/17 prescaler is used.
IF_P
0
1
IF Prescaler
8/9
16/17
Maximum Frequency
800 MHz
800 MHz
2.5.3 RF_CPP -- RF PLL Charge Pump Polarity
RF_CPP
0
1
RF Charge Pump Polarity
Negative
Positive (Default)
2.5.4 IF_CPP -- IF PLL Charge Pump Polarity
For a positive phase detector polarity, which is normally the case, set this bit to 1. Otherwise set this bit for a negative phase
detector polarity.
IF_CPP
0
1
IF Charge Pump Polarity
Negative
Positive
2.5.5 OSC_OUT Oscillator Output Buffer Enable
OSC_OUT
0
1
OSCout Pin
Disabled (High Impedance)
Buffered output of OSCin pin
L
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