參數資料
型號: LNBK10SP
廠商: 意法半導體
英文描述: LNB SUPPLY AND CONTROL VOLTAGE REGULATOR PARALLEL INTERFACE
中文描述: LNB電源與控制穩(wěn)壓器并行接口
文件頁數: 3/18頁
文件大?。?/td> 205K
代理商: LNBK10SP
TABLE A: PIN CONFIGURATIONS
SYMBOL
NAME
FUNCTION
PIN NUMBER vs SALES TYPE (LNBK)
20CR 20PD 10SP 11SP 12SP 13SP 14SP 15SP 16SP
V
CC1
Supply Input 1
15V to 27V supply. It is
automatically selected
when V
OUT
= 13 or 14V
22V to 27V supply. It is
automatically selected
when V
OUT
= 18 or 19V
See truth tables for voltage
and port selection. In
stand-by mode this port is
powered by the MI pin via
the internal Bypass Switch
Logic control input: See
truthtable
1
2
1
1
1
1
1
1
1
V
CC2
Supply Input 2
2
3
2
2
2
2
2
2
2
LNBA
Output Port
3
4
3
3
3
3
3
3
3
VSEL
Output Voltage
Selection: 13 or
18V (typ)
4
5
4
4
4
4
4
4
4
EN
Port Enable
Logic control input: See
truthtable
Logic control input: See
truthtable
Circuit Ground. It is
internally connected to the
die frame
5
6
5
5
5
5
5
5
5
OSEL
Port Selection
7
7
9
NA
NA
NA
NA
NA
NA
GND
Ground
8
1
10
11
20
6
6
6
6
6
6
6
ENT
22 KHz Tone
Enable
Logic control input: See
truthtable
9
13
7
7
7
7
7
7
7
CEXT
External Capacitor
Timing capacitor used by
the Dynamic Overload
Protection. Typical
application is 4.7
μ
F for a
1200 ms cycle
ExternalModulation Input.
Needs DC decoupling to
the AC source. If not used,
can be left open.
Logic control input: See
truthtable
10
14
8
8
8
8
8
8
8
EXTM
External
Modulation
11
15
NA
NA
NA
9
NA
9
9
LLC
Line Length
Compens (+1V typ)
12
16
NA
NA
9
NA
9
NA
10
OLF
Over Load Flag
Logic output (open
Collector). Normally in
HIGH IMPEDANCE,goes
LOW when current or
thermal overload occurs.
In stand-by mode, the
voltage on MI is routed to
LNBA pin. Canbe left
open if bypass functionis
not needed
See truth tables for voltage
and port selection.
13
17
NA
9
NA
NA
10
10
NA
MI
Master Input
14
18
NA
10
10
10
NA
NA
NA
LNBB
Output Port
15
19
10
NA
NA
NA
NA
NA
NA
NOTE: The limited pin availability of the PowerSO-10 package leads to drop some functions.
LNBK10 SERIES - LNBK20
3/18
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