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參數(shù)資料
| 型號： | LNBS21PD-TR |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | SIGN, NO SMOKING, 175X125MM, SAV; RoHS Compliant: NA |
| 中文描述： | LNB電源與控制集成電路升壓轉(zhuǎn)換器和I2C接口 |
| 文件頁數(shù)： | 16/19頁 |
| 文件大?。?/td> | 637K |
| 代理商： | LNBS21PD-TR |
LNBS21
16/19
Figure 34 :
Output Voltage Transient Response
from 13V to 18V
Figure 35 :
Output Voltage Transient Response
from 13V to 18V
TERMAL DESIGN NOTES
During normal operation, this device dissipates
some power. At maximum rated output current
(500mA), the voltage drop on the linear regulator
lead to a total dissipated power that is of about
1.7W. The heat generated requires a suitable
heatsink to keep the junction temperature below
the
overtemperature
Assuming
a
40°C
temperature
Set-Top-Box case, the total Rthj-amb has to be
less than 50°C/W.
protection
threshold.
inside
the
While this
through-hole power package that can be attached
to a small heatsink or to the metallic frame of the
receiver, a surface mount power package must
rely on PCB solutions whose thermal efficiency is
often limited.
The simplest solution is to use a
large, con-tinuous copper area of the GND layer to
dissipate the heat coming from the IC body.
can be easily
achieved using a
The SO-20 package of this IC has 4 GND pins that
are
not
just
intended
connec-tion, but also to provide a low thermal
resistance path between the silicon chip and the
PCB heatsink. Given an Rthj-c equal to 15°C/W,
a maximum of
35°C/W
heatsink. This figure is achieved if a minimum of
25cm2 copper area is placed just below the IC
for
electrical
GND
are left to the PCB
body. This area can be the inner GND layer of a
multi-layer PCB, or, in a dual layer PCB, an
unbroken GND area even on the opposite side
where the IC is placed. In both cases, the thermal
path between the IC GND pins and the dissipating
copper area must exhibit a low thermal resistance.
In figure 4 , it is shown a suggested layout for the
SO-20 package with a dual layer PCB, where the
IC Ground pins and the square dissipating area
are thermally connected through 32 vias holes,
filled
by
solder.
This
L=50mm, achieves an Rthc-a of about 25°C/W.
Different
layouts
are
principles, however, suggest to keep the IC and its
ground pins approximately in the middle of the
dissipating area; to provide as many vias as
possible; to de-sign a dissipating area having a
shape as square as possible and not interrupted
by other copper traces.
Due to presence of an exposed pad connected to
GND below the IC
body, the PowerSO-20
package has a Rthj-c much lower than the SO-20,
only 2°C/W. As a result, much lower copper area
must be provided to dissipate the same power and
minimum of 12cm2 copper area is enough, see
figure 5.
arrangement,
when
possible,
too.
Basic
V
CC
=12V, I
O
=50mA, VSEL=from 0 to 1, EN=1
V
CC
=12V, I
O
=50mA, VSEL=from 1 to 0, EN=1
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