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參數(shù)資料
| 型號： | LP2995 |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | Hex Inverters 14-SO -40 to 85 |
| 中文描述： | DDR終端穩(wěn)壓器 |
| 文件頁數(shù)： | 3/13頁 |
| 文件大?。?/td> | 291K |
| 代理商： | LP2995 |
Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
(Note 1)
PVIN, AVIN, VDDQ to GND
Storage Temp. Range
Junction Temperature
SO-8 Thermal Resistance (
θ
JA
)
LLP-16 Thermal Resistance (
θ
JA
)
0.3V to +6V
65C to +150C
150C
151C/W
51C/W
Lead Temperature (Soldering, 10 sec)
ESD Rating (Note 7)
260C
1kV
Operating Range
Junction Temp. Range (Note 5)
AVIN to GND
PVIN to GND
0C to +125C
2.2V to 5.5V
2.2V to AVIN
Electrical Characteristics
type
apply over the full
Operating Temperature Range
(T
J
= 0C to +125C). Unless otherwise specified,
AVIN = PVIN = 2.5V, VDDQ = 2.5V (Note 6).
Specifications with standard typeface are for T
J
= 25C and limits in
boldface
Symbol
Parameter
Conditions
Min
1.21
15
20
Typ
1.235
0
Max
1.26
15
20
Units
V
mV
V
REF
VOS
VTT
V
REF
Voltage
V
TT
Output Voltage Offset
I
REF_OUT
= 0mA
I
OUT
= 0A
(Note 2)
I
OUT
= 0 to 1.5A
I
OUT
= 0 to 1.5A
I
REF
= 5μA to +5μA
V
TT
/V
TT
Load Regulation
(Note 3)
0.5
0.5
5
100
250
%
Z
VREF
Z
VDDQ
I
q
V
REF
Output Impedance
VDDQ Input Impedance
Quiescent Current
k
k
μA
I
OUT
= 0A
(Note 4)
400
Note 1:
Absolute maximum ratings indicate limits beyond which damage to the device may occur. Operating range indicates conditions for which the device is
intended to be functional, but does not guarantee specific performance limits. For guaranteed specifications and test conditions see Electrical Characteristics. The
guaranteed specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed
test conditions.
Note 2:
V
TT
offset is the voltage measurement defined as V
TT
subtracted from V
REF
.
Note 3:
Load regulation is tested by using a 10ms current pulse and measuring V
TT
.
Note 4:
Quiescent current defined as the current flow into AVIN.
Note 5:
At elevated temperatures, devices must be derated based on thermal resistance. The device in the SO-8 package must be derated at
θ
JA
= 151 C/W
junction to ambient with no heat sink. The device in the LLP-16 must be derated at
θ
JA
= 51 C/W junction to ambient.
Note 6:
Limits are 100% production tested at 25C. Limits over the operating temperature range are guaranteed through correlation using Statistical Quality Control
(SQC) methods. The limits are used to calculate National’s Average Outgoing Quality Level (AOQL).
Note 7:
The human body model is a 100pF capacitor discharged through a 1.5k
resistor into each pin.
L
www.national.com
3
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