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參數(shù)資料
| 型號： | LP365N |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 比較器 |
| 英文描述： | Micropower Programmable Quad Comparator |
| 中文描述： | QUAD COMPARATOR, 6000 uV OFFSET-MAX, 1000 ns RESPONSE TIME, PDIP16 |
| 封裝： | PLASTIC, DIP-16 |
| 文件頁數(shù)： | 3/10頁 |
| 文件大?。?/td> | 209K |
| 代理商： | LP365N |
Electrical Characteristics
(Continued) (Note 8) High power V
S
e
g
15V, I
SET
e
100
m
A
LP365A
LP365
Symbol
Parameter
Conditions
Tested
Limit
(Note 5)
Design
Limit
(Note 6)
Tested
Limit
(Note 5)
Design
Limit
(Note 6)
Units
(Limit)
Typ
Typ
V
OS
Input Offset
Voltage
V
CM
e
0V,
R
S
e
100
1
3
6
3
6
9
mV
(Max)
I
OS
Input Offset
Current
V
CM
e
0V
LP265
5
50
100
10
90
200
nA
10
90
500
(Max)
I
B
Input Bias
Current
V
CM
e
0V
LP265
60
200
500
80
300
500
nA
80
300
800
(Max)
A
VOL
Large Signal
Voltage Gain
R
L
e
15k
500
100
100
500
100
100
V/mV
(Min)
V
CM
Input Common-
Mode Voltage
Range
b
15
b
15
b
15
b
15
V
(Max)
13
13
13
13
V
(Min)
CMRR
Common-Mode
Rejection Ratio
b
15V
s
V
CM
s
13V
85
75
70
80
75
70
dB
(Min)
PSRR
Supply Voltage
Rejection Ratio
g
10V
s
V
S
sg
15V
80
70
70
75
70
70
dB
(Min)
I
S
Supply Current
All Inputs
e
0V,
R
L
e
%
, LP265
2.6
3
3.3
2.8
3.5
3.7
mA
(Max)
2.8
3.5
4.3
V
OH
Output Voltage
High
V
C
e
5V,
V
E
e
0V,
R
L
e
100k
V
4.9
4.5
4.9
4.5
(Min)
V
OL
Output Voltage
Low
V
E
e
0V
0.4
0.4
0.4
0.4
V
(Max)
I
SINK
Output Sink
Current
V
E
e
0V,
V
O
e
0.4V
10
8
5.5
7.5
6
4
mA
(Min)
I
LEAK
Output Leakage
Current
V
C
e
15V,
V
E
eb
15V
5
50
5000
5
50
5000
nA
(Max)
t
R
Response Time
V
CC
e
5V,
V
E
e
0V,
R
L
e
5k,
C
L
e
10 pF
(Note 7)
1.0
1.0
m
s
Note 1:
The input voltage is not allowed to go 0.3V above V
a
or
b
0.3V below V
b
as this will turn on a parasitic transistor causing large currents to flow through
the device.
Note 2:
Short circuits from the output to V
a
may cause excessive heating and eventual destruction. The current in the output leads and the V
E
lead should not be
allowed to exceed 30 mA. The output should not be shorted to V
b
if V
E
s
(V
b
)
a
7V.
Note 3:
For operating at elevated temperatures, these devices must be derated based on a thermal resistance of
i
jA
and T
j
max. T
j
e
T
A
a
i
jA
P
D
.
Note 4:
Boldface numbers apply at temperature extremes.
All other numbers apply at T
A
e
T
j
e
25
§
C. V
a
e
5V, V
b
e
0V, I
SET
e
10
m
A, R
L
e
100k, and
V
C
e
5V as shown in the Typical Connection diagram.
Note 5:
Guaranteed and 100% production tested.
Note 6:
Guaranteed (but not 100% production tested) over the operating temperature and supply voltage ranges. These limits are not used to calculate out-going
quality levels.
Note 7:
The response time specified is for a 100 mV input step with 5 mV overdrive.
Note 8: Boldface numbers apply at temperature extremes.
All other numbers apply at T
A
e
T
j
e
25
§
C. V
a
e a
15V, V
b
eb
15V, I
SET
e
100
m
A, R
L
e
100k, and
V
C
e
5V as shown in the Typical Connection diagram.
Note 9:
See AN-450 ‘‘Surface Mounting Methods and Their Effect on Product Reliability’’ for other methods of soldering surface mount devices.
Note 10:
Human body model, 1.5 k
X
in series with 100 pF.
3
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