參數(shù)資料
型號: LP3985IBL-5.0
廠商: NATIONAL SEMICONDUCTOR CORP
元件分類: 基準電壓源/電流源
英文描述: GT 3C 3#16S SKT RECP WALL RM
中文描述: 5 V FIXED POSITIVE LDO REGULATOR, 0.1 V DROPOUT, PBGA5
封裝: 0.995 MM HEIGHT, MICRO, SMD-5
文件頁數(shù): 2/17頁
文件大?。?/td> 570K
代理商: LP3985IBL-5.0
Block Diagram
10136401
Pin Description
Name
V
EN
GND
V
OUT
V
IN
BYPASS
* micro SMD
A1
B2
C1
C3
A3
SOT
3
2
5
1
4
Function
Enable Input Logic, Enable High
Common Ground
Output Voltage of the LDO
Input Voltage of the LDO
Optional Bypass Capacitor for Noise
Reduction
* The pin numbering scheme for the micro SMD package was revised in April 2002 to conform to JEDEC standard. Only the pin numbers were
revised. No changes to the physical location of the inputs/outputs were made. For reference purposes, the obsolete numbering scheme had VEN
as pin 1, GND as pin 2, VOUT as pin 3, VIN as pin 4, and BYPASS as pin 5.
Connection Diagrams
SOT 23-5 Package (MF)
5 Bump micro SMD Package (BPA05, BLA05, TLA05)
10136407
Top View
See NS Package Number MF05A
10136470
Top View
See NS Package Number BPA05, BLA05, TLA05
L
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LP3985IBLX-2.85 制造商:未知廠家 制造商全稱:未知廠家 功能描述:VOLT REGULATOR|FIXED|+2.85V|CMOS|BGA|5PIN|PLASTIC