參數(shù)資料
型號: LP61L1008S-15
廠商: AMIC Technology Corporation
元件分類: SRAM
英文描述: 128K X 8 BIT 3.3V HIGH SPEED CENTER POWER CMOS SRAM
中文描述: 128K的× 8位高速3.3V的中心功耗CMOS SRAM
文件頁數(shù): 2/13頁
文件大?。?/td> 142K
代理商: LP61L1008S-15
LP61L1008 Series
128K X 8 BIT 3.3V HIGH SPEED CENTER POWER CMOS SRAM
(June, 2002, Version 2.0)
1
AMIC Technology, Inc.
Features
n
Single 3.3V
±
10% power supply
n
Access times: 12/15 ns (max.)
n
Current: Operating: 180mA (max.)
Standby:
n
Full static operation, no clock or refreshing required
n
All inputs and outputs are directly TTL compatible
n
Center Power/Ground Pin Configuration
n
Common I/O using three-state output
n
Output enable and two chip enable inputs for easy
application
n
Data retention voltage: 2.0V (min.)
n
Available in 32-pin SOJ 300 mil and 32-pin sTSOP
packages
Product Family
General Description
5mA (max.)
The LP61L1008 is a high speed 1,048,576-bit static
random access memory organized as 131,072
words by 8 bits and operates on a single 3.3V power
supply.
Inputs and three-state outputs are TTL compatible and
allow for direct interfacing with common system bus
structures.
The chip enable input is provided for POWER-DOWN
and device enable and an output enable input is included
for easy interfacing.
Data retention is guaranteed at a power supply voltage
as low as 2.0V.
Power Dissipation
Standby
(I
SB1
, Typ.)
Product
Family
Operating
Temperature
VCC
Range
Speed
Data Retention
(I
CCDR
, Typ.)
Operating
(I
CC2
, Typ.)
Package
Type
LP61L1008
0
°
C~70
°
C
3.0V~3.6V
12/15 ns
10
μ
A
20
μ
A
66mA
32L SOJ
32L sTSOP
1. Typical values are measured at VCC = 3.0V, T
A
= 25
°
C and not 100% tested.
2. Data retention current VCC = 2.0V.
Pin Configuration
n
SOJ
n
sTSOP
A0
A1
A2
A3
CE
I/O
1
I/O
2
VCC
GND
I/O
3
I/O
4
WE
A4
A5
A6
A8
A7
A9
A10
A11
A12
I/O
5
I/O
6
VCC
I/O
7
I/O
8
OE
A13
A14
A15
A16
GND
L
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
A15
A14
A13
OE
I/O
7
I/O
6
VSS
VCC
I/O
5
I/O
4
A12
A16
LP61L1008X
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A0
A1
A2
A3
CE
I/O
0
VCC
VSS
I/O
2
I/O
3
WE
A4
A5
A6
A7
A11
A10
A9
A8
I/O
1
~
~
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