參數(shù)資料
型號(hào): LP61L1024V-15
廠商: AMIC Technology Corporation
英文描述: 128K X 8 BIT 3.3V HIGH SPEED LOW VCC CMOS SRAM
中文描述: 128K的× 8位3.3V的高速低虛擬通道連接CMOS SRAM的
文件頁(yè)數(shù): 11/16頁(yè)
文件大?。?/td> 178K
代理商: LP61L1024V-15
LP61L1024
(August, 2002, Version 2.1)
10
AMIC Technology, Inc.
AC Test Conditions
Input Pulse Levels
0V to 3.0V
Input Rise and Fall Time
3 ns
Input and Output Timing Reference Levels
1.5V
Output Load
See Figures 1 and 2
+3.3V
I/O
350
320
30pF*
* Including scope and jig.
+3.3V
I/O
350
320
5pF*
* Including scope and jig.
Data Retention Characteristics
(T
A
= 0
°
C to 70
°
C)
Figure 1. Output Load
Figure 2. Output Load for t
CLZ1
,
t
CLZ2
, t
OHZ
, t
OLZ
, t
CHZ1
,
t
CHZ2
, t
WHZ
, and t
OW
Symbol
Parameter
Min.
Max.
Unit
Conditions
V
DR1
VCC for Data Retention
2
3.6
V
CE1
VCC - 0.2V
CE2
VCC - 0.2V or
CE2
0.2V
V
DR2
2
3.6
V
CE2
0.2V
CE1
VCC - 0.2V or
CE1
0.2V
I
CCDR1
Data Retention Current
-
5
mA
VCC = 3.0V
CE1
VCC - 0.2V
CE2
VCC - 0.2V
V
IN
VCC - 0.2V or
V
IN
0.2V
I
CCDR2
-
5
mA
VCC = 3.0V
CE2
0.2V
CE1
0.2V
V
IN
VCC - 0.2V or
V
IN
0.2V
t
CDR
Chip Disable to Data Retention Time
0
-
ns
See Retention Waveform
t
R
Operation Recovery Time
5
-
ms
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