參數(shù)資料
型號: LP61L1024X-12
廠商: AMIC Technology Corporation
英文描述: 128K X 8 BIT 3.3V HIGH SPEED LOW VCC CMOS SRAM
中文描述: 128K的× 8位3.3V的高速低虛擬通道連接CMOS SRAM的
文件頁數(shù): 3/16頁
文件大?。?/td> 178K
代理商: LP61L1024X-12
LP61L1024
(August, 2002, Version 2.1)
2
AMIC Technology, Inc.
Pin Configurations
n
SOJ
n
TSOP / TSSOP
n
CSP (Chip Size Package)
36-pin Top View
Block Diagram
VCC
GND
DECODER
256 X 4096
MEMORY ARRAY
INPUT
DATA
CIRCUIT
COLUMN I/O
CONTROL
CIRCUIT
A0
A14
A15
A16
I/O
1
I/O
8
CE2
CE1
OE
WE
Pin Description
Pin No.
Symbol
Description
2 - 12, 23,
25 - 28, 31
A0 - A16
Address Inputs
29
WE
Write Enable
24
OE
Output Enable
22
CE1
Chip Enable
30
CE2
Chip Enable
1
NC
No Connection
13 - 15, 17 - 21
I/O
1
- I/O
8
Data Input/Outputs
32
VCC
Power Supply
16
GND
Ground
NC
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O
1
I/O
2
I/O
3
I/O
4
GND
I/O
5
I/O
6
I/O
7
I/O
8
CE1
A10
OE
A9
A8
A13
WE
CE2
A15
VCC
A11
L
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
L
1
16
17
32
Pin No.
Pin
Name
Pin No.
Pin
Name
1
2
A9
3
4
5
6
7
8
9
10
11
12
13
14
30
29
28
27
26
25
24
22
19
21
20
23
18
17
A8
A13
CE2
A15
VCC
NC
I/O
8
A16
A14
A12
A7
A6
A3
A2
A1
A0
I/O
1
I/O
2
GND
I/O
4
I/O
5
I/O
6
I/O
7
I/O
3
A11
WE
CE1
15
16
31
32
A5
A4
A10
OE
A0
I/O
4
I/O
5
GND
VCC
I/O
6
I/O
7
A9
A10
OE
A11
CE1
A12
A13
A14
A16
NC
NC
A15
I/O
3
I/O
2
I/O
1
I/O
0
GND
VCC
A1
A2
NC
WE
NC
A5
A4
A3
A6
A7
A8
6
5
4
3
2
1
A
B
C
D
E
F
G
H
相關PDF資料
PDF描述
LP61L1024X-15 128K X 8 BIT 3.3V HIGH SPEED LOW VCC CMOS SRAM
LP61L1024 128K X 8 BIT 3.3V HIGH SPEED LOW VCC CMOS SRAM
LP61L1024S-12 128K X 8 BIT 3.3V HIGH SPEED LOW VCC CMOS SRAM
LP61L1024S-15 128K X 8 BIT 3.3V HIGH SPEED LOW VCC CMOS SRAM
LP61L1024U-15 128K X 8 BIT 3.3V HIGH SPEED LOW VCC CMOS SRAM
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